Semiconductor device having turn-on and turn-off capabilities

Claim 2

A latching semiconductor device providing insulated gate control over turn-on and turn-off comprising: a wafer of semiconductor material having first and second major surfaces and including first, second, third and fourth regions successively joined together, said first and third regions being of one conductivity type and being spaced apart by said second region, said second and fourth regions being of an opposite conductivity type and being spaced apart by said third region, a fifth region of said opposite conductivity type extending into said first region and being spaced from said second region; said second region extending to both said first major surface and said second major surface; said first and fifth regions extending to said first major surface and being spaced from said second major surface by said second region; said third and fourth regions extending to said second major surface and being spaced from said first major surface by said second region; said first region including a first channel region adjacent said first surface between said fifth region and said second region; said third region including a second channel region adjacent said second surface between said fourth region and said second region; a first main electrode disposed over said first major surface in ohmic contact with said first and fifth regions; a second main electrode disposed over said second major surface in ohmic contact with said fourth region and being electrically insulated from said third region; when said device has a bias applied across said first and second main electrodes and is conducting in a latched state in a first polarity, said first channel region, when rendered conductive, serving to turn said device off; a first insulated gate electrode disposed on said first major surface over said first channel region to control conduction between said fifth and second regions through said first channel region; and a second insulated gate electrode disposed on said second major surface over said second channel region to control conduction between said second and fourth regions through said second channel region.

Claim 3

An insulated gate turn-off latching semiconductor device comprising: a wafer of semiconductor material having first and second major surfaces and including first, second, third and fourth regions successively joined together, said first and third regions being of one conductivity type and being spaced apart by said second region, said second and fourth regions being of an opposite conductivity type and being spaced apart by said third region, said first, third and fourth regions each comprising a plurality of spaced apart segments, a plurality of fifth region segments of said opposite conductivity type extending into said first region segments and being spaced from said second region; said second region extending to both said first major surface and said second major surface; said first and fifth region segments each extending to said first major surface and being spaced from said second major surface by said second region; said third and fourth region segments extending to said second major surface and being spaced from said first major surface by said second region; a first main electrode disposed over said first major surface in ohmic contact with said first region segments and said fifth region segments; a second main electrode disposed over said second major surface in ohmic contact with said fourth region segments, and being electrically insulated from said third region; and said device including: a plurality of first cells distributed along said first major surface with a first cell repeat distance measured along said first major surface of less than the minimum thickness of said second region, each of said first cells including a portion of said second region and one of said first region segments and one of said fifth region segments and comprising conductor-insulator-semiconductor type means for controlling the transport of majority carriers of said opposite type between said fifth region segment and said second region and, when said device has a bias across its first and second main electrodes and is conducting in a latched state in a first polarity, said conductor-insulator-semiconductor type means serving as a turn-off control mechanism for said device; a plurality of second cells distributed along said second major surface with a second cell repeat distance measured along said second major surface of less than the minimum thickness of said second region, each of said second cells including a portion of said second region and one of said third region segments and one of said fourth region segments and comprising conductor-insulator-semiconductor type means for controlling the transport of majority carriers of said opposite type between said second main electrode and said second region.

Claim 4

An insulated gate turn-off latching semiconductor device comprising: a wafer of semiconductor material having first and second major surfaces and including first, second, third and fourth regions successively joined together, said first and third regions being of one conductivity type and being spaced apart by said second region, said second and fourth regions being of an opposite conductivity type and being spaced apart by said third region, said first, third and fourth regions each comprising a plurality of spaced apart segments, a plurality of fifth region segments of said opposite conductivity type extending into said first region segments and being spaced from said second region; said second region extending to both said first major surface and said second major surface; said first and fifth region segments each extending to said first major surface and being spaced from said second major surface by said second region; said third and fourth region segments extending to said second major surface and being spaced from said first major surface by said second region; a first main electrode disposed over said first major surface in ohmic contact with said first region segments and said fifth region segments; a second main electrode disposed over said second major surface in ohmic contact with said fourth region segments, and being electrically insulated from said third region; and said device including: a plurality of first cells distributed along said first major surface with a first cell repeat distance measured along said first major surface of less than the minimum thickness of said second region, each of said first cells including a portion of said second region and one of said first region segments and one of said fifth region segments and comprising conductor-insulator-semiconductor type means for controlling the transport of majority carriers of said opposite type between said fifth region segment and said second region and, when said device has a bias across its first and second main electrodes and is conducting in a latched state in a first polarity, said conductor-insulator-semiconductor type means serving as a turn-off control mechanism for said device; a plurality of second cells distributed along said second major surface with a second cell repeat distance measured along said second major surface of less than the minimum thickness of said second region, each of said second cells including a portion of said second region and one of said third region segments and one of said fourth region segments and comprising conductor-insulator-semiconductor type means for controlling the transport of majority carriers of said opposite type between said second main electrode and said second region.

Claim 5

The semiconductor device recited in claim 1 wherein: said first major surface is substantially planar; and said first channel region is aligned directly across said wafer from said second channel region whereby a straight line perpendicular to the plane of said first major surface which passes through said first channel region also passes through the portion of said second channel region with which it is directly aligned.

Claim 6

The semiconductor device recited in claim 1 wherein said first channel region has a lower doping concentration than the rest of said first region; and said second channel region has a lower doping concentration than the rest of said third region.

Claim 7

The semiconductor device recited in claim 1 wherein: said first major surface is substantially planar; and said first channel region includes first and second portion disposed adjacent two opposing sides of said first region and said first region includes a central portion extending to said first surface and into contact with said first electrode between said first and second portions of said first channel region to provide a regenerative current path extending directly through said wafer between said first main electrode and said second main electrode whereby said regenerative current path is substantially perpendicular to the plane of said first major surface.

Claim 8

The semiconductor device recited in claim 5 wherein: said second channel region surrounds said fourth region.

Claim 9

The semiconductor device recited in claim 6 wherein said fourth region is aligned directly across said wafer from said central portion of said first region as part of said direct regenerative current path.

Claim 10

The semiconductor device recited in claim 5 wherein said central portion of said first region is aligned directly across said wafer from said fourth region as part of said direct regenerative current path.

Claim 11

The semiconductor device recited in claim 1 wherein: said fourth and fifth regions each comprise a plurality of separate, spaced-apart segments.

Claim 12

The semiconductor device recited in claim 9 wherein: said first and third regions each comprise a plurality of spaced apart portions each respectively containing one of said portions of said fifth and fourth regions.

Claim 13

The semiconductor device recited in claim 1 wherein: said first major surface is substantially planar; each of said first cells includes a first channel region; each of said second cells includes a second channel region; and each of said first channel regions is aligned directly across said wafer from one of said second channel regions whereby a straight line perpendicular to the plane of said first major surface which passes through said first channel region also passes through the portion of said second channel region with which it is aligned.

Claim 14

The semiconductor device recited in claim 11 wherein: said first channel region has a lower doping concentration than the rest of said first region; and said second channel region has a lower doping concentration than the rest of said third region.

Claim 15

The semiconductor device recited in claim 11 wherein: said first channel region includes first and second portions disposed adjacent two opposing sides of said first region and said first region includes a central portion extending to said first surface and into contact with said first electrode between said first and second portions of said first channel region to provide a regenerative current path extending directly through said wafer between said first main electrode and said second main electrode.

Claim 16

The semiconductor device recited in claim 13 wherein said fourth region is aligned directly across said wafer from said central portion of said first region as part of said direct regenerative current path.

Claim 17

The semiconductor device recited in claim 14 wherein said fourth region is aligned directly across said wafer from said central portion of said first region as part of said direct regenerative current path.

Claim 18

The semiconductor device recited in claim 15 wherein said central portion of said first region is aligned directly across said wafer from said fourth region as part of said direct regenerative current path.