US4816878A
Expired / Lapsed
US
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Negative resistance semiconductor device
Assignee: Toyota Central R&D Labs Inc
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Filing: 1986-11-13
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Granted: 1989-03-28
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Expires: 2006-11-13
Abstract
Abstract A semiconductor device having a superlattice structure, which comprises at least one unit structure including first and third semiconductor layers as quantum well layers, and a second semiconductor layer as a barrier layer, which are arranged alternately on each other is described. The first semiconductor layer has a higher impurity concentration than the third semiconductor layer and has a quantum energy level determined by its thickness. The third semiconductor layer is of a thickness having quantum energy levels, one of which is lower than that of the first semiconductor layer and the second of which is equal to or higher than that of the first semiconductor layer. The second semiconductor layer is of a thickness which allows electrons existing at the second quantum energy level of the third semiconductor layer to transfer easily from the third to the first semiconductor layer. An increase in voltage applied to the semiconductor device causes electrons to transfer to the first semiconductor layer through the second quantum energy level of the third semiconductor layer to reduce the mobility of electrons in the first semiconductor layer, thus causing the semiconductor device to develop a negative resistance.
Inventors
- 👤 Hiroyuki Kano
- 👤 Masafumi Hashimoto
- 👤 Nobuhiko Sawaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:39
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D48/00; H10D48/30; H10D48/38; H10D62/00; H10D62/80; H10D62/81; H10D62/815; H10D62/8161; H10D62/8162; H10D62/8164
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
319 words
A negative resistance semiconductor device having a superlattice structure comprising: at least one unit structure comprised of first, second and third semiconductor layers; said first and third semiconductor layers being quantum well layers having an impurity concentration, and said second semiconductor layer being a barrier layer, said first, second and third semiconductor layers being superposed on each other so that the second semiconductor layer is between the first and third semiconductor layers; said impurity concentration of said first semiconductor layer being higher than said impurity concentration of said third semiconductor layer, and said first semiconductor having a quantum energy level determined by a layer thickness thereof; said third semiconductor layer being of a thickness having first and second quantum energy levels, said first quantum energy level being lower than said quantum energy level of said first semiconductor layer and said second quantum energy level being equal to or higher than said quantum energy level of said first semiconductor layer; said second semiconductor layer being of a thickness which allows electrons existing at said second quantum energy level of said third semiconductor layer to transfer easily from said second quantum energy level of said third semiconductor layer to said quantum energy level of said first semiconductor layer; and at least one pair of electrodes for applying voltage to said superlattice structure in a direction perpendicular to the direction of thickness of said superlattice so as to allow electrons at each of said quantum energy level to flow through said quantum well layers; whereby an increase in voltage applied to said superlattice structure causes electrons at said first quantum energy level of said third semiconductor layer to transfer to said quantum energy level of said first semiconductor layer through said second quantum energy level of said third semiconductor layer to reduce the mobility of electrons in said first semiconductor layer due to the higher impurity concentration of said first semiconductor layer.
Claim 2
Dependent Claim
319 words
A negative resistance semiconductor device having a superlattice structure comprising: at least one unit structure comprised of first, second and third semiconductor layers; said first and third semiconductor layers being quantum well layers having an impurity concentration, and said second semiconductor layer being a barrier layer, said first, second and third semiconductor layers being superposed on each other so that the second semiconductor layer is between the first and third semiconductor layers; said impurity concentration of said first semiconductor layer being higher than said impurity concentration of said third semiconductor layer, and said first semiconductor having a quantum energy level determined by a layer thickness thereof; said third semiconductor layer being of a thickness having first and second quantum energy levels, said first quantum energy level being lower than said quantum energy level of said first semiconductor layer and said second quantum energy level being equal to or higher than said quantum energy level of said first semiconductor layer; said second semiconductor layer being of a thickness which allows electrons existing at said second quantum energy level of said third semiconductor layer to transfer easily from said second quantum energy level of said third semiconductor layer to said quantum energy level of said first semiconductor layer; and at least one pair of electrodes for applying voltage to said superlattice structure in a direction perpendicular to the direction of thickness of said superlattice so as to allow electrons at each of said quantum energy level to flow through said quantum well layers; whereby an increase in voltage applied to said superlattice structure causes electrons at said first quantum energy level of said third semiconductor layer to transfer to said quantum energy level of said first semiconductor layer through said second quantum energy level of said third semiconductor layer to reduce the mobility of electrons in said first semiconductor layer due to the higher impurity concentration of said first semiconductor layer.
Claim 3
Dependent Claim
78 words
A semiconductor device according to claim 1, wherein said at least one unit structure further comprises at least one set of fourth and fifth semiconductor layers, said fourth semiconductor layer being identical in composition to said second semiconductor layer and said fifth semiconductor layer being identical in composition to said first semiconductor layer; said fourth and fifth semiconductor layers being arranged such that said fourth semiconductor layer is in contact with said first and said fifth semiconductor layers.
Claim 4
Dependent Claim
40 words
A semiconductor device according to claim 1, wherein said at least one unit structure further comprises first and second outer layers, said first outer layer contacting said first semiconductor layer and a second outer layer contacting said third semiconductor layer.
Claim 5
Dependent Claim
29 words
A semiconductor device according to claim 1, wherein each of said quantum well layers is comprised of GaAs and said barrier layer is comprised of Al x Ga.sub.(1-x) As.
Claim 6
Dependent Claim
27 words
A semiconductor device according to claim 1, wherein said impurity concentration of said first semiconductor layer is at least ten times that of said third semiconductor layer.
Claim 7
Dependent Claim
48 words
A semiconductor device according to claim 1, wherein the thickness of said barrier layer is not less than 30 Å and not more than 100 Å and the thickness of each of said quantum well layers is not less than 30 Å and not more than 250 Å.
Claim 8
Dependent Claim
223 words
A semiconductor device according to claim 3, further comprising: (a) a semi-insulated GaAs substrate; (b) an undoped n-type GaAs layer superposed on said semi-insulated GaAs substrate; (c) an undoped Al 0 .3 Ga 0 .7 As layer superposed on said n-type GaAs layer; (d) said at least one unit structure being superposed on said undoped Al 0 .3 Ga 0 .7 As layer; (e) an undoped n-type Al 0 .3 Ga 0 .7 As layer or a doped n-type Al 0 .3 Ga 0 .7 As layer with a low impurity concentration superposed on said at least one unit structure; (f) at least one n-type GaAs layer doped with a high impurity concentration superposed on said undoped n-type Al 0 .3 Ga 0 .7 As layer; (g) at least two n-type ohmic electrodes comprised of a metal superposed on said at least one n-type GaAs layer doped with a high impurity concentration; wherein said first outer layer, said second semiconductor layer, and said second outer layer of said at least one unit structure are selected from the group consisting of undoped n-type Al 0 .3 Ga 0 .7 As and doped n-type Al 0 .3 Ga 0 .7 As having a low impurity concentration; and said first semiconductor layer and said third semiconductor layer are doped n-type GaAs with a high impurity concentration.
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USPTO Annuity & Maintenance Windows
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| 3.5 Years (Year 4) | 1992-03-27 | 1992-09-26 | 1993-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-27 | 1996-09-26 | 1997-03-28 | $3760.00 | Window Closed / Lapsed |
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