US4814977A
Expired / Lapsed
US
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Apparatus and method for direct memory to peripheral and peripheral to memory data transfers
Assignee: S&C Electric Co
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Filing: 1986-10-29
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Granted: 1989-03-21
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Expires: 2006-10-29
Abstract
Abstract A multi-microprocessor implemented data processing system having a single cycle data transfer capability for its memory mapped peripheral devices is described. A host or controlling microprocessor provides address and control signals for memory accesses. In addition, it also determines that a peripheral operation is desired. When this occurs, a command is sent to the selected peripheral and a memory cycle, fetch or store, for the data transfer is initiated. The address bus is provided with the memory address for the needed data and a special decode that indicates the unique nature of this memory access. Logic circuit means are provided to detect the special decode and to intercept the data bus at the appropriate point in the bus cycle in response thereto. The logic circuit means is adapted to then responsively apply the correct control signals to the peripheral to enable the desired data transfer after the data bus has been intercepted.
Inventors
- 👤 Joseph P. Buonomo
- 👤 Raymond E. Losinger
- 👤 Burton L. Oliver
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:42
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/063; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3877; G06F9/3879
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
275 words
A multiprocessor system comprising: a bus; a memory connected to said bus; a peripheral device connected to said bus; a primary processor connected to said bus, said primary processor including an internal store, said primary processor outputting a plurality of function code signals; and control means connected to said bus for outputting a plurality of conditioning signals in response to said function code signals, said conditioning signals controlling the execution and direction of a direct data transfer between said peripheral device and said memory without intermediate storage of said data in said internal store of said primary processor, said direct data transfer executed in response to said conditioning signals, said bus tightly coupled to said peripheral device during said direct data transfer; said control means further comprising a function code signal decoder means, an address decocer means, and a write gate means; said function code signal decoder means producing as an output a conditioning signal in response to said function code signals indicating when said primary processor is issuing a command or transferring data; said address decoder means producing as an output a conditioning signal when said primary processor is addressing said peripheral device; said conditioning signals produced as the output of said function code signal decoder means and the output of said address decoder means together enable the selection of said peripheral device for a read or write operation between said peripheral device and said memory; said write gate means producing a conditioning signal in response to an output of write signals from said primary processor and an output of said function code decoder means indicating read or write status to said peripheral device.
Claim 2
Dependent Claim
275 words
A multiprocessor system comprising: a bus; a memory connected to said bus; a peripheral device connected to said bus; a primary processor connected to said bus, said primary processor including an internal store, said primary processor outputting a plurality of function code signals; and control means connected to said bus for outputting a plurality of conditioning signals in response to said function code signals, said conditioning signals controlling the execution and direction of a direct data transfer between said peripheral device and said memory without intermediate storage of said data in said internal store of said primary processor, said direct data transfer executed in response to said conditioning signals, said bus tightly coupled to said peripheral device during said direct data transfer; said control means further comprising a function code signal decoder means, an address decocer means, and a write gate means; said function code signal decoder means producing as an output a conditioning signal in response to said function code signals indicating when said primary processor is issuing a command or transferring data; said address decoder means producing as an output a conditioning signal when said primary processor is addressing said peripheral device; said conditioning signals produced as the output of said function code signal decoder means and the output of said address decoder means together enable the selection of said peripheral device for a read or write operation between said peripheral device and said memory; said write gate means producing a conditioning signal in response to an output of write signals from said primary processor and an output of said function code decoder means indicating read or write status to said peripheral device.
Claim 3
Dependent Claim
108 words
The system of claim 1 wherein said conditioning signals include a first conditioning signal and a second conditioning signal outputted in response to a first function code signal and a said second funtion code signal respectively, a first state of said first conditioning signal conditioning said peripheral device for a direct data transfer and a second state of said first conditioning signal conditioning said peripheral device for no direct data transfer, a first state of said second conditioning signal conditioning said peripheral device to accept data from said memory and a second state of said second conditioning signal conditioning said peripheral device to transfer data to said memory.
Claim 4
Dependent Claim
100 words
The system of claim 2 further comprising: a plurality of bidirectional buffers connected to said bus, said buffers intermediately storing said data during said direct data transfer, said conditioning signals including a third conditioning signal outputted in response to a third function code signal, said third conditioning signal controlling the direction of data transfer through said buffers, a first state of said third conditioning signal conditioning said buffers to transfer data from said memory to said peripheral device and a second state of said third conditioning signal conditioning said buffers to transfer data from said peripheral device to said memory.
Claim 5
Dependent Claim
14 words
The system of claim 1 wherein said peripheral device is emulated by a coprocessor.
Claim 6
Dependent Claim
276 words
A multiprocessor system comprising: a bus; an actual memory connected to said bus; a peripheral device connected to said bus; a primary processor connected to said bus, said primary processor including an internal store, said primary processor outputting a plurality of function code signals; and control means connected to said bus for outputting a plurality of conditioning signals in response to said function code signals, said conditioning signals controlling the execution and direction of a direct data transfer between said peripheral device and said actual memory without intermediate storage of said data in said internal store of said primary processor, said direct data transfer executed in response to said conditioning signals, said primary processor addressing said actual memory during said direct data transfer; said control means further comprising a function code signal decoder means, an address decoder means, and a write gate means; said function code signal decoder means producing as an output a conditioning signal in response to said function code signals indicating when said primary processor is issuing a command or transferring data; said address decoder means producing as an output a conditioning signal when said primary processor is addressing said peripheral device; said conditioning signals produced as the output of said function code signal decoder means and the output of said address decoder means together enable the selection of said peripheral device for a read or write operation between said peripheral device and said memory; said write gate means producing a conditioning signal in response to an output of write signals from said primary processor and an output of said function code decoder means indicating read or write status to said peripheral device.
Claim 7
Dependent Claim
276 words
A multiprocessor system comprising: a bus; an actual memory connected to said bus; a peripheral device connected to said bus; a primary processor connected to said bus, said primary processor including an internal store, said primary processor outputting a plurality of function code signals; and control means connected to said bus for outputting a plurality of conditioning signals in response to said function code signals, said conditioning signals controlling the execution and direction of a direct data transfer between said peripheral device and said actual memory without intermediate storage of said data in said internal store of said primary processor, said direct data transfer executed in response to said conditioning signals, said primary processor addressing said actual memory during said direct data transfer; said control means further comprising a function code signal decoder means, an address decoder means, and a write gate means; said function code signal decoder means producing as an output a conditioning signal in response to said function code signals indicating when said primary processor is issuing a command or transferring data; said address decoder means producing as an output a conditioning signal when said primary processor is addressing said peripheral device; said conditioning signals produced as the output of said function code signal decoder means and the output of said address decoder means together enable the selection of said peripheral device for a read or write operation between said peripheral device and said memory; said write gate means producing a conditioning signal in response to an output of write signals from said primary processor and an output of said function code decoder means indicating read or write status to said peripheral device.
Claim 8
Dependent Claim
110 words
The system of claim 5 wherein said conditioning signals include a first conditioning signal and a second conditioning signal outputted in response to a first function code signal and a said second function code signal respectively, a first state of said first conditioning signal conditioning said peripheral device for a direct data transfer and a second state of said first conditioning signal conditioning said peripheral device for no direct data transfer, a first state of said second conditioning signal conditioning said peripheral device to accept data from said actual memory and a second state of said second conditioning signal conditioning said peripheral device to transfer data to said actual memory.
Claim 9
Dependent Claim
101 words
The system of claim 6 further comprising: a plurality of bidirectional buffers connected to said bus, said buffers intermediately storing said data during said direct data transfer, said conditioning signals including a third conditioning signal outputted in response to said function code signals, said third conditioning signal controlling the direction of data transfer through said buffers, a first state of said third conditioning signal conditioning said buffers to transfer data from said actual memory to said peripheral device and a second state of said third conditioning signal conditioning said buffers to transfer data from said peripheral device to said actual memory.
Claim 10
Dependent Claim
14 words
The system of claim 5 wherein said peripheral device is emulated by a coprocessor.
Claim 11
Independent Claim
310 words
A method for transferring data in a multiprocessor system, said multiprocessor system including a bus, a memory connected to said bus, a peripheral device connected to said bus, a primary processor connected to said bus and including an internal store, and a control means connected to said bus, said control means further comprising a function code signal decoder means, an address decoder means, and a write gate means, said method comprising the steps of: outputting a plurality of function code signals from said primary processor; outputting a plurality of conditioning signals from said control means in response to said function code signals, said conditioning signals controlling the execution and direction of a direct data transfer between said peripheral device and said memory without intermediate storage of said data in said internal store of said primary processor; producing a conditioning signal from said function code signal decoder means in response to said function code signals from said primary processor indicating when said primary processor is issuing a command or transferring data; producing a conditioning signal from said address decoder means when said primary processor is addressing said peripheral device; selecting said peripheral device for a read or write operation between said peripheral device and said memory under control of said conditioning signals produced by said function code signal decoder means and said address decoder means; producing a conditioning signal from said write gate means in response to the output of write signals from said primary processor and the output of said function code signal decoder means indicating read or write status to said peripheral device; directly transferring data between said peripheral device and said memory in response to said conditioning signals without intermediate storage of said data in said internal store of said primary processor; and maintaining said bus tightly coupled with said peripheral device during said direct transfer of data.
Claim 12
Independent Claim
310 words
A method for transferring data in a multiprocessor system, said multiprocessor system including a bus, a memory connected to said bus, a peripheral device connected to said bus, a primary processor connected to said bus and including an internal store, and a control means connected to said bus, said control means further comprising a function code signal decoder means, an address decoder means, and a write gate means, said method comprising the steps of: outputting a plurality of function code signals from said primary processor; outputting a plurality of conditioning signals from said control means in response to said function code signals, said conditioning signals controlling the execution and direction of a direct data transfer between said peripheral device and said memory without intermediate storage of said data in said internal store of said primary processor; producing a conditioning signal from said function code signal decoder means in response to said function code signals from said primary processor indicating when said primary processor is issuing a command or transferring data; producing a conditioning signal from said address decoder means when said primary processor is addressing said peripheral device; selecting said peripheral device for a read or write operation between said peripheral device and said memory under control of said conditioning signals produced by said function code signal decoder means and said address decoder means; producing a conditioning signal from said write gate means in response to the output of write signals from said primary processor and the output of said function code signal decoder means indicating read or write status to said peripheral device; directly transferring data between said peripheral device and said memory in response to said conditioning signals without intermediate storage of said data in said internal store of said primary processor; and maintaining said bus tightly coupled with said peripheral device during said direct transfer of data.
Claim 13
Dependent Claim
112 words
The method of claim 9 wherein said outputting of conditioning signals includes outputting a first conditioning signal and a second conditioning signal from said control means in response to a first function code signal and a second function code signal respectively, a first state of said first conditioning signal conditioning said peripheral device for a direct data transfer and a second state of said first conditioning signal conditioning said peripheral device for no direct data transfer, a first state of said second conditioning signal conditioning said peripheral device to accept data from said memory and a second state of said conditioning signal conditioning said peripheral device to transfer data to said memory.
Claim 14
Dependent Claim
119 words
The method of claim 10 further including a plurality of bidirectional buffers connected to said bus, wherein said outputting of conditioning signals includes outputting a third conditioning signal from said control means in response to a third function code signal, said buffers intermediately storing said data during said direct data transfer, said third conditioning signal controlling the direction of data transfer through said buffers, said buffers intermediately storing said data during said direct transfer of data, a first state of said third conditioning signal conditioning said buffers to transfer data from said memory to said peripheral device and a second state of said third conditioning signal conditioning said buffers to transfer data from said peripheral device to said memory.
Claim 15
Dependent Claim
14 words
The method of claim 9 wherein said peripheral device is emulated by a coprocessor.
Claim 16
Independent Claim
312 words
A method for transferring data in a multiprocessor system, said multiprocessor system including a bus, an actual memory connected to said bus, a peripheral device connected to said bus, a primary processor connected to said bus and including an internal store, and a control means connected to said bus, said control means further comprising a function code signal decoder means, an address decoder means, and a write gate means, said method comprising the steps of: outputting a plurality of function code signals from said primary processor; outputting a plurality of conditioning signals from said control means in response to said function code signals, said conditioning signals controlling the execution and direction of a direct data transfer between said peripheral device and said actual memory without intermediate storage of said data in said internal store of said primary processor; producing a conditioning signal from said function code signal decoder means in response to said function code signals from said primary processor indicating when said primary processor is issuing a command or transferring data; producing a conditioning signal from said address decoder means when said primary processor is addressing said peripheral device; selecting said peripheral device for a read or write operation between said peripheral device and said memory under control of said conditioning signals produced by said function code signal decoder means and said address decoder means; producing a conditioning signal from said write gate means in response to an output of write signals from said primary processor and the output of said function code signal decoder means indicating read or write status to said peripheral device; directly transferring data between said peripheral device and said actual memory in response to said conditioning signals without intermediate storage of said data in said internal store of said primary processor; and addressing said actual memory by said primary processor during said direct transferring of data.
Claim 17
Independent Claim
312 words
A method for transferring data in a multiprocessor system, said multiprocessor system including a bus, an actual memory connected to said bus, a peripheral device connected to said bus, a primary processor connected to said bus and including an internal store, and a control means connected to said bus, said control means further comprising a function code signal decoder means, an address decoder means, and a write gate means, said method comprising the steps of: outputting a plurality of function code signals from said primary processor; outputting a plurality of conditioning signals from said control means in response to said function code signals, said conditioning signals controlling the execution and direction of a direct data transfer between said peripheral device and said actual memory without intermediate storage of said data in said internal store of said primary processor; producing a conditioning signal from said function code signal decoder means in response to said function code signals from said primary processor indicating when said primary processor is issuing a command or transferring data; producing a conditioning signal from said address decoder means when said primary processor is addressing said peripheral device; selecting said peripheral device for a read or write operation between said peripheral device and said memory under control of said conditioning signals produced by said function code signal decoder means and said address decoder means; producing a conditioning signal from said write gate means in response to an output of write signals from said primary processor and the output of said function code signal decoder means indicating read or write status to said peripheral device; directly transferring data between said peripheral device and said actual memory in response to said conditioning signals without intermediate storage of said data in said internal store of said primary processor; and addressing said actual memory by said primary processor during said direct transferring of data.
Claim 18
Dependent Claim
111 words
The method of claim 13 wherein said outputting of conditioning signals includes outputting a first conditioning signal and a second conditioning signal in response to a first function code signal and a second function code signal respectively, a first state of said first conditioning signal conditioning said peripheral device for a direct data transfer and a second state of said first conditioning signal conditioning said peripheral device for no direct data transfer, a first state of said second conditioning signal conditioning said peripheral device to accept data from said actual memory and a second state of said second conditioning signal conditioning said peripheral device to transfer data to said actual memory.
Claim 19
Dependent Claim
121 words
The method of claim 14 further including a plurality of bidirectional buffers connected to said bus, wherein said outputting of conditioning signals includes outputting a third conditioning signal from said control means in response to a third function code signal, said buffers intermediately storing said data during said direct data transfer, said third conditioning signal controlling the direction of data transfer through said buffers, said buffers intermediately storing said data during said direct transfer of data, a first state of said third conditioning signal conditioning said buffers to transfer data from said actual memory to said peripheral device and a second state of said third conditioning signal conditioning said buffers to transfer data from said peripheral device to said actual memory.
Claim 20
Dependent Claim
14 words
The method of claim 13 wherein said peripheral device is emulated by a coprocessor.
References Cited (Backward Citations)
US3482948A
Cited
US4038642A
Cited
US4056848A
Cited
US4128876A
Cited
US4099236A
Cited
US4122520A
Cited
US4245300A
Cited
US4270167A
Cited
US4346439A
Cited
US4249240A
Cited
EP0021365A2
Cited
US4371932A
Cited
US4516199A
Cited
US4481580A
Cited
US4426679A
Cited
US4475155A
Cited
US4454575A
Cited
US4400772A
Cited
US4476522A
Cited
US4413613A
Cited
US4471427A
Cited
US4547849A
Cited
US4543627A
Cited
US4590556A
Cited
US4679166A
Cited
US4677433A
Cited
US4589067A
Cited
US4591982A
Cited
US4598356A
Cited
US4648034A
Cited
US4695945A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-20 | 1992-09-19 | 1993-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-20 | 1996-09-19 | 1997-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-20 | 2000-09-19 | 2001-03-21 | $7700.00 | Window Closed / Lapsed |