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US4814842A Expired / Lapsed US ⏱️ 0.0 years remaining

Thin film transistor utilizing hydrogenated polycrystalline silicon

Assignee: Canon Inc
•
Filing: 1988-05-25
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Granted: 1989-03-21
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Expires: 2008-05-25
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Abstract

Abstract A thin film transistor comprises a substrate, a semiconductor layer comprising a polycrystalline silicon containing 3 atomic % or less of hydrogen provided on said substrate, a source region and a drain region provided in the surface part of said semiconductor layer, an insulating layer provided on said semiconductor layer at the portion between these two regions, a gate electrode provided on said insulating layer, a source electrode forming an electrical contact with the source region and a drain electrode forming an electrical contact with the drain region, the overlapping portions between said gate electrode through the insulating layer beneath said gate electrode and the source region and between said gate electrode through the insulating layer beneath said gate electrode and the drain region begin 2000 ANGSTROM or less in width.

Inventors

  • 👤 Katsumi Nakagawa
  • 👤 Toshiyuki Komatsu
  • 👤 Yutaka Hirai
  • 👤 Satoshi Omata
  • 👤 Yoshiyuki Osada
  • 👤 Takashi Nakagiri

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 15:57
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6729; H10D30/673; H10D30/6731; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 129 words
A thin film transistor comprising a substrate, a semiconductor layer comprising a polycrystalline silicon containing 3 atomic % or less of hydrogen provided on said substrate, a source region and a drain region provided in the surface part of said semiconductor layer, an insulating layer provided on said semiconductor layer between said source region and said drain region, a gate electrode provided on said insulating layer, a source electrode forming an electrical contact with said source region and a drain electrode forming an electrical contact with said drain region, wherein said insulating layer and said gate electrode have portions overlapping said source region and said drain region and the portion overlapping said source region and the portion overlapping said drain region are each 2000 Å or less in width.
Claim 2
Dependent Claim 129 words
A thin film transistor comprising a substrate, a semiconductor layer comprising a polycrystalline silicon containing 3 atomic % or less of hydrogen provided on said substrate, a source region and a drain region provided in the surface part of said semiconductor layer, an insulating layer provided on said semiconductor layer between said source region and said drain region, a gate electrode provided on said insulating layer, a source electrode forming an electrical contact with said source region and a drain electrode forming an electrical contact with said drain region, wherein said insulating layer and said gate electrode have portions overlapping said source region and said drain region and the portion overlapping said source region and the portion overlapping said drain region are each 2000 Å or less in width.
Claim 3
Dependent Claim 16 words
A thin film transistor according to claim 1, wherein the substrate is made of a glass.
Claim 4
Dependent Claim 17 words
A thin film transistor according to claim 1, wherein the substrate is made of a heat-resistant plastic.
Claim 5
Dependent Claim 17 words
A thin film transistor according to claim 1, wherein the substrate is made of a heat-resistant ceramic.
Claim 6
Dependent Claim 19 words
A thin film transistor according to claim 1, wherein the overlapping portions are 1500 Å or less in width.
Claim 7
Dependent Claim 19 words
A thin film transistor according to claim 1, wherein the overlapping portiona are 1200 Å or less in width.

References Cited (Backward Citations)

US3191061A Cited
US3290569A Cited
US3818426A Cited
US4081817A Cited
US4217374A Cited
US4409605A Cited
US4176365A Cited
US4351856A Cited
US4409607A Cited
DE3241959A1 Cited
JPS6170A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-03-20 1992-09-19 1993-03-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-03-20 1996-09-19 1997-03-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-03-20 2000-09-19 2001-03-21 $7700.00 Window Closed / Lapsed

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