Patent US4813043A successfully refreshed from Google Patents.
US4813043A
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Semiconductor test device
Assignee: Mitsubishi Electric Corp
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Filing: 1987-02-20
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Granted: 1989-03-14
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Expires: 2007-02-20
Abstract
Abstract A semiconductor test device including a function test algorithmic pattern generator which comprises: an ALU unit with shift-in function for conducting a predetermined arithmetical and logical operation against the base data or the output of an ALU output register; the ALU output register being designed to store the output of the ALU and output a function test algorithmic pattern; and a parity detection circuit which conducts a parity detection against an arbitrary group of bits of the ALU output register, and the detection output is input into a shift-in input of the ALU.
Inventors
- 👤 Hideshi Maeno
- 👤 Tetsuo Tada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:44
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318385; G01R31/31813; G06; G06F; G06F7/00; G06F7/58; G06F7/582; G06F7/584; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F2207/00; G06F2207/58; G06F2207/581; G06F2207/583
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
103 words
A test device for generating algorithmic test patterns comprising: an ALU unit with shift-in means for generating and storing algorithmic test patterns by conducting predetermined arithmetic and logic operations on input data to said ALU unit; parity detection means for generating a parity detection bit from selected parity bits of said algorithmic test patterns generated by said ALU unit, said parity detection bit is input into said ALU unit for providing said shift-in means; and selection means for selecting between input reference data and said algorithmic test patterns from said ALU unit, said selecting means provides said input data to said ALU unit.
Claim 2
Dependent Claim
103 words
A test device for generating algorithmic test patterns comprising: an ALU unit with shift-in means for generating and storing algorithmic test patterns by conducting predetermined arithmetic and logic operations on input data to said ALU unit; parity detection means for generating a parity detection bit from selected parity bits of said algorithmic test patterns generated by said ALU unit, said parity detection bit is input into said ALU unit for providing said shift-in means; and selection means for selecting between input reference data and said algorithmic test patterns from said ALU unit, said selecting means provides said input data to said ALU unit.
Claim 3
Dependent Claim
31 words
The test device of claim 1, wherein said ALU unit comprises ALU means for generating said algorithmic test patterns and an output register for storing and outputting said algoriithmic test patterns.
Claim 4
Dependent Claim
41 words
The test device of claim 1, wherein said parity detection means comprises: bit selection means for selecting said selected parity bits; and logic operation means for generating said parity detection bit from said selected parity bits and said algorithmic test patterns.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-13 | 1992-09-12 | 1993-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-13 | 1996-09-12 | 1997-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-13 | 2000-09-12 | 2001-03-14 | $7700.00 | Window Closed / Lapsed |