Dynamic RAM device having a separate test mode capability

Claim 2

A dynamic RAM device comprising: a memory array including a plurality of memory cells placed on intersections of a plurality of word lines and a plurality of data lines; of selecting means for selecting multiple ones said memory cells in response to the selection of respective ones of said word lines and data lines comprising a first selecting circuit for selecting a word line in accordance with an address signal which is synchronized with a row address strobe signal, and a second selecting circuit for selecting a data line in accordance with an address signal which is synchronized with a column address strobe signal; an output circuit for reading data from respective ones of said multiple memory cells selected by said selecting means during a normal operating mode of said RAM device, said output circuit implementing data reading in response to a logic "high" level write enable signal; and a test circuit which, during a test mode which is exclusive of said normal operating mode, writes data having the same value to the selected memory cells, verifies as to whether or not data which is read out of the selected memory cells are consistent with a predetermined data, and provides a resultant verification output, said test mode being set in response to said column address strobe signal being at a logic "low" level and said write enable signal being at a logic "low" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.

Claim 3

A dynamic RAM device according to claim 1 further comprising: an external input terminal for writing data; and an external output terminal for reading out data, said external input terminal receiving data to be written in said device during said normal operating mode when there is no testing and during said test mode, said external output terminal outputting data being read out of said device during said normal operating mode and during said test mode.

Claim 4

A dynamic RAM device including a plurality of memory cells and test means for testing said dynamic RAM device, said dynamic RAM device further comprising: selecting means for selecting a memory cell in accordance with an address signal and an address signal which is synchronized with a row address strobe signal and a column address strobe signal, respectively; output means which reads data from said selected memory cell in response to a logic "high" level write enable signal; and mode setting means which is coupled to said test means and which sets said test means into a test mode upon detection of said column address strobe signal at a logic "low" level and said write enable signal at a logic "low" level when said row address strobe signal is at a transitional level corresponding to a falling edge.

Claim 5

A dynamic RAM device including a plurality of memory cells and test means for testing said dynamic RAM device, said dynamic RAM device further comprising: selecting means for selecting a memory cell in accordance with an address signal and an address signal which is synchronized with a row address strobe signal and a column address strobe signal, respectively; output means which reads data from said selected memory cell in response to a logic "high" level write enable signal; and mode setting means which is coupled to said test means and which sets said test means into a test mode upon detection of said column address strobe signal at a logic "low" level and said write enable signal at a logic "low" level when said row address strobe signal is at a transitional level corresponding to a falling edge.

Claim 6

A dynamic RAM device according to claim 3, wherein said mode setting means terminates the test mode in said test means upon detection of said column address strobe signal at a logic "low" level and said write enable signal at a logic "high" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.

Claim 7

A dynamic RAM device according to claim 3, wherein said mode setting means terminates the test mode in said test means upon detection of said row address strobe signal at a logic "low" level when said column address strobe signal is at, a logic "high" level and said write enable signal is at a logic "high" level in a memory cycle.

Claim 8

A dynamic RAM device including a plurality of memory cells and test means for testing said dynamic RAM device said dynamic RAM device further comprising: selecting means which selects a memory cell corresponding to an address signal and an address signal which is synchronized with a row address strobe signal and a column address strobe signal, respectively; input means for writing data into a selected memory cell in accordance with a write enable signal being at a logic "low" level; and mode setting means which is coupled to said test means and which sets said test means into a test mode upon detection of said column address strobe signal at a logic "low" level, said write enable signal at a logic "low" level and a first address signal at a first predetermined logic level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.

Claim 9

A dynamic RAM device including a plurality of memory cells and test means for testing said dynamic RAM device said dynamic RAM device further comprising: selecting means which selects a memory cell corresponding to an address signal and an address signal which is synchronized with a row address strobe signal and a column address strobe signal, respectively; input means for writing data into a selected memory cell in accordance with a write enable signal being at a logic "low" level; and mode setting means which is coupled to said test means and which sets said test means into a test mode upon detection of said column address strobe signal at a logic "low" level, said write enable signal at a logic "low" level and a first address signal at a first predetermined logic level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.

Claim 10

A dynamic RAM device according to claim 6, wherein said mode setting means terminates the test mode in said test means upon detection of said column address strobe signal at a logic "low" level, said write enable signal at a logic "low" level, and said first address signal at a second predetermined logic level when said row address strobe signal is at said falling edge.

Claim 11

A dynamic RAM device according to claim 6, wherein said first address signal corresponds to the bit of a plurality of address signal bits of said RAM device positionally resulting in an address signal having the highest binary order.

Claim 12

A dynamic RAM device according to claim 6, further including output means for read-out of stored data, and wherein said test means, when in said test mode, writes data of the same value into a plurality of memory cells, verifies as to whether or not data which is read out of said memory cells are consistent with a predetermined data and provides a resultant verification output, said test means includes output modes indicative of verification results, said mode selecting means selects one of said output modes of said test means in accordance with a voltage level of a second address signal when said mode setting means sets said test means into said test mode.

Claim 13

A dynamic RAM device including a plurality of memory cells and test means for testing said dynamic RAM device, said dynamic RAM device comprising: selecting means for selecting a memory cell in correspondence to an address signal and an address signal which is synchronized with a row address strobe signal and a column address strobe signal, respectively; input means for writing data into a selected memory cell in response to a logic "low" level write enable signal; and mode setting means which is coupled to said test means and which sets said test means into a test mode upon detection of said column address strobe signal at a logic "low" level and said write enable signal at a logic "low" level when said row address strobe signal is at a transitional logical level corresponding to a falling edge.

Claim 14

A dynamic RAM device including a plurality of memory cells and test means for testing said dynamic RAM device, said dynamic RAM device comprising: selecting means for selecting a memory cell in correspondence to an address signal and an address signal which is synchronized with a row address strobe signal and a column address strobe signal, respectively; input means for writing data into a selected memory cell in response to a logic "low" level write enable signal; and mode setting means which is coupled to said test means and which sets said test means into a test mode upon detection of said column address strobe signal at a logic "low" level and said write enable signal at a logic "low" level when said row address strobe signal is at a transitional logical level corresponding to a falling edge.

Claim 15

A dynamic RAM device according to claim 10, wherein said mode setting means terminates the test mode in said test means upon detection of said column address strobe signal at a logic "low" level and said write enable signal at a logic "high" level when said row address strobe signal is at said falling edge.

Claim 16

A dynamic RAM device comprising: a memory array including a plurality of memory cells placed on intersections of a plurality of word lines and a plurality of data lines; selecting means for selecting multiple memory cells in said plurality of memory cells; input means for inputting input data to selected ones of said memory cells; test signal generating means for generating a test signal in response to a column address strobe signal being at a logic "low" level and a write enable signal being at a logic "low" level when a row address strobe signal is at a transitional logic level corresponding to a falling edge; and test means, coupled to said test signal generating means for testing said dynamic RAM device in response to said test signal.

Claim 17

A dynamic RAM device comprising: a memory array including a plurality of memory cells placed on intersections of a plurality of word lines and a plurality of data lines; selecting means for selecting multiple memory cells in said plurality of memory cells; input means for inputting input data to selected ones of said memory cells; test signal generating means for generating a test signal in response to a column address strobe signal being at a logic "low" level and a write enable signal being at a logic "low" level when a row address strobe signal is at a transitional logic level corresponding to a falling edge; and test means, coupled to said test signal generating means for testing said dynamic RAM device in response to said test signal.

Claim 18

A dynamic RAM device according to claim 10, wherein said test signal generating means includes means for storing said test signal.

Claim 19

A dynamic RAM device according to claim 13, wherein said storing means stops storing said test signal when said column address strobe signal is at a logic "low" level and said write enable signal is at a logic "high" level when said row address strobe signal is at said falling edge.

Claim 20

A dynamic RAM device according to claim 13, wherein said storing means stops storing said test signal when said row address strobe signal is at a logic "low" level when said column address strobe signal is at a logic "high" level and said write enable signal is at a logic "high" level in a memory cycle.

Claim 21

A dynamic RAM device comprising: a memory array including a plurality of memory cells placed on intersections of a plurality of word lines and a plurality of data lines; selecting means for selecting multiple memory cells in said plurality of memory cells; output means for outputting output data from selected ones of said memory cells; test signal generating means for generating a test signal in response to a column address strobe signal being at a logic "low" level and a write enable signal being at a logic "low" level when a row address strobe signal is at a transitional logic level corresponding to a falling edge; and test means, coupled to said test signal generating means, for testing said dynamic RAM device in response to said test signal.

Claim 22

A dynamic RAM device comprising: a memory array including a plurality of memory cells placed on intersections of a plurality of word lines and a plurality of data lines; selecting means for selecting multiple memory cells in said plurality of memory cells; output means for outputting output data from selected ones of said memory cells; test signal generating means for generating a test signal in response to a column address strobe signal being at a logic "low" level and a write enable signal being at a logic "low" level when a row address strobe signal is at a transitional logic level corresponding to a falling edge; and test means, coupled to said test signal generating means, for testing said dynamic RAM device in response to said test signal.

Claim 23

A dynamic RAM device according to claim 16, wherein said test signal generating means includes means for storing said test signal.

Claim 24

A dynamic RAM device according to claim 17, wherein said storing means stops storing said test signal when said column address strobe signal is at a logic "low" level and said write enable signal is at a logic "high" level when said row address strobe signal is at said falling edge.

Claim 25

A dynamic RAM device comprising: A memory array including a plurality of one MOS transistor memory cells, each being coupled between a respective one of a plurality of word and data lines which are arranged as rows and columns, respectively; selecting means for selecting multiple ones of said memory cells in response to the selection of respective word lines and data lines, comprising a first selecting circuit for selecting a word line in response to a row address signal which is concurrent with a row address strobe signal and a second selecting circuit for selecting a data line in response to a column address signal which is concurrent with a column address strobe signal; input means for writing data into respective ones of said multiple memory cells selected by said selecting means during a WRITE phase of a normal operating mode in response to a write enable signal having a first binary logic state; output means for reading data form said respective ones of said multiple memory cells selected by said selecting means during a READ phase of said normal operating mode in response to a write enable signal having a second binary logic state which is the complement of said first logic state; and a test circuit which, during a test mode which is exclusive of said normal operating mode, writes data having the same binary value to the selected memory cells, verifies as to whether or not data which is read out of the selected memory cells corresponds to that of predetermined data stored therein, and provides an output indicative of the result verified, said test mode being set in response to both said column address strobe signal and said write enable signal being in said first binary logic state when said row address strobe signal is at a transitional logic state condition corresponding to a pulse trailing edge.

Claim 26

A dynamic RAM device comprising: A memory array including a plurality of one MOS transistor memory cells, each being coupled between a respective one of a plurality of word and data lines which are arranged as rows and columns, respectively; selecting means for selecting multiple ones of said memory cells in response to the selection of respective word lines and data lines, comprising a first selecting circuit for selecting a word line in response to a row address signal which is concurrent with a row address strobe signal and a second selecting circuit for selecting a data line in response to a column address signal which is concurrent with a column address strobe signal; input means for writing data into respective ones of said multiple memory cells selected by said selecting means during a WRITE phase of a normal operating mode in response to a write enable signal having a first binary logic state; output means for reading data form said respective ones of said multiple memory cells selected by said selecting means during a READ phase of said normal operating mode in response to a write enable signal having a second binary logic state which is the complement of said first logic state; and a test circuit which, during a test mode which is exclusive of said normal operating mode, writes data having the same binary value to the selected memory cells, verifies as to whether or not data which is read out of the selected memory cells corresponds to that of predetermined data stored therein, and provides an output indicative of the result verified, said test mode being set in response to both said column address strobe signal and said write enable signal being in said first binary logic state when said row address strobe signal is at a transitional logic state condition corresponding to a pulse trailing edge.

Claim 27

A dynamic RAM device according to claim 19, wherein said first and second binary logic states consist of the logic "0" level and the logic "1" level, respectively.