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Patent US4811287A successfully refreshed from Google Patents.
US4811287A
Expired / Lapsed
US
⏱️ 0.0 years remaining
EEPROM mounting device
Assignee: RTX Corp
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Filing: 1986-10-27
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Granted: 1989-03-07
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Expires: 2006-10-27
Abstract
Abstract Apparatus (82) for providing write protection for EEPROMs (10) intended as a replacement for installed ROM devices, includes write protection circuitry (54) mounted on one surface (88) of a circuit board (84), the other surface (86) receiving the EEPROM, providing a direct plug-in module for retrofit of installed ROM devices.
Inventors
- 👤 Bertram F. Kupersmith
- 👤 Michael B. Herzog
- 👤 James D. Fraser
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:25
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/22
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
226 words
Apparatus (82) for providing write protect mounting of an EEPROM (10) having a pin array (12-28) with an output enable pin (24) and a power supply pin (26), to the mounting pad array of a ROM socket disposed within ROM spatial clearance dimensions on a system board, comprising: circuit board means (84), having a first surface (86) with a array of pads (90) adapted to receive the EEPROM pin array, and having a second surface (88) with an array of pins (92) adapted to be inserted into the ROM socket pads to provide electrical connection of the EEPROM pins, other than the EEPROM output enable pin, to the system board ROM socket; and protection circuit means (54), mounted on said second surface of said circuit board means, and responsive at inputs thereof to signals appearing at the ROM socket output enable pad (62) and the EEPROM power supply pin, and having a signal output connected to the EEPROM output enable pin, said circuit means presenting a write enabling logic state signal to the EEPROM output enable pin in the presence of a write enabling logic state signal at the ROM socket output enable pad concurrent with a minimum voltage signal magnitude at the EEPROM power supply pin, and for presenting a write disabling logic state signal to the EEPROM output enable pin at all other times.
Claim 2
Dependent Claim
226 words
Apparatus (82) for providing write protect mounting of an EEPROM (10) having a pin array (12-28) with an output enable pin (24) and a power supply pin (26), to the mounting pad array of a ROM socket disposed within ROM spatial clearance dimensions on a system board, comprising: circuit board means (84), having a first surface (86) with a array of pads (90) adapted to receive the EEPROM pin array, and having a second surface (88) with an array of pins (92) adapted to be inserted into the ROM socket pads to provide electrical connection of the EEPROM pins, other than the EEPROM output enable pin, to the system board ROM socket; and protection circuit means (54), mounted on said second surface of said circuit board means, and responsive at inputs thereof to signals appearing at the ROM socket output enable pad (62) and the EEPROM power supply pin, and having a signal output connected to the EEPROM output enable pin, said circuit means presenting a write enabling logic state signal to the EEPROM output enable pin in the presence of a write enabling logic state signal at the ROM socket output enable pad concurrent with a minimum voltage signal magnitude at the EEPROM power supply pin, and for presenting a write disabling logic state signal to the EEPROM output enable pin at all other times.
Claim 3
Dependent Claim
147 words
The apparatus of claim 1, wherein said protection circuit means comprises: threshold detection means (56), responsive to the signals appearing at the EEPROM power supply pin, for providing a first logic state signal in the presence of a voltage signal magnitude at the EEPROM power supply pin which is greater than a minimum signal magnitude; and signal comparison means, including a signal comparator (58) connected (64) to said threshold detection means and a signal buffer (60) connected (70) to said signal comparator and to the ROM socket output enable pad, for providing in the presence of said first logic state signal concurrent with said write enabling logic state signal at the ROM socket output enable pad, said write enabling logic state signal to the EEPROM output enable pin, and for providing said write disabling logic state signal to the EEPROM output enabling pin at all other times.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-06 | 1992-09-05 | 1993-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-06 | 1996-09-05 | 1997-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-06 | 2000-09-05 | 2001-03-07 | $7700.00 | Window Closed / Lapsed |