Quadruply extended time multiplexed information bus for reducing the `pin out` configuration of a semiconductor chip package

Claim 1

A digital processor system comprising: processor means for processing of data according to program instructions; memory means including a memory array means for storing according to memory addresses, the data and program instructions: Interface means coupled between said processor means and said memory means for transferring the data and programmed instructions, said interface means comprising: control means responsive to said processor means and said memory means for providing control signals in response to the processor means and said memory means; a quadruply extended time multiplex information bus means having a first preselected number of bits in width for transferring data and program instructions having a second preselected number of bits in width greater that the first preselected number of bits between said processor means and said memory means; memory addressing means coupled to said quadruply extended time multiplex information bus for receiving memory address and the data and programs instructions and includes; a first register means for providing memory address of the data to the memory array means, a second register means for providing memory addresses of the program instructions to the memory array means, boththe first and second register means being coupled to said control means and in response to the control signals alter the contents of said first and second register means by incrementing or decrementing the register contents of the first register means, switch means for connecting either the first or second register means to the memory array means in response to a preselected member of the control signals to store the data and program instructions in the memory array means thereby.