Gate array arrangement

Claim 2

A gate array arrangement formed on a semiconductor chip comprising: a plurality of I/O cells aligned in a rectangular formation with a first predetermined pitch, each I/O cell having a power source output terminal and a ground terminal for outputting voltage by an externally provided wire through an electric power pad, said terminals being located at identical positions in each of said I/O cells; a plurality of basic cells aligned in a plurality of rows extending in a space defined by said I/O cells, said rows being aligned with a second predetermined pitch; first and second bus lines formed on a first electrode layer and extending in parallel in a space between said I/O cells and said basic cells; a first interconnecting power line formed on a separate layer insulated from said first electrode layer and extending between said power source terminal and said first bus line; a second interconnecting ground line formed on a separate layer insulated from said first electrode layer and extending between said ground terminal and said second bus line, said first and second interconnecting lines supplying power to the first and second bus lines and being aligned side-by-side and parallel to one another; a third interconnecting power line formed on a separate layer insulated from said first electrode layer and extending straight from said first bus line and crossing said basic cells; a fourth interconnecting ground line formed on the first electrode layer and extending straight from said second bus line and crossing said basic cells, wherein said third and fourth interconnecting lines are aligned side-by-side and parallel to one another, and said basic cells are supplied from said third and fourth interconnecting lines, and wherein said first and second predetermined pitches are determined independently of one another.

Claim 3

A gate array arrangement formed on a rectangular chip having first, second, third, and fourth sides, in which the first and second sides are orthogonal to each other and third and fourth sides are respectively parallel to said first and second sides, said gate array arrangement comprising: a plurality of I/O cells aligned along four sides of said rectangular semiconductor chip with a first predetermined pitch, each I/O cell having a power source output terminal and a ground terminal for outputting voltage by an externally provided wire through an electric power pad, said terminals being located at identical positions in each of said I/O cells; a plurality of basic cells aligned in a plurality of rows extending in a space defined by said I/O cells, said rows being parallel to said first side of said chip and aligned with a second predetermined pitch; first and second bus lines formed on a first electrode layer, and both extending in parallel in a space between said I/O cells and said basic cells in a rectangular formation with four sides thereof being parallel to said four sides of said chip; a first interconnecting power line formed on a separate layer insulated from said first electrode layer and extending parallel to said first side of said chip and between said power source terminal of I/O cells aligned along said second and fourth sides of said chip and said first bus line; a second interconnecting ground line formed on a separate layer insulated from said first electrode layer, and extending parallel to said first side and said chip and between said ground terminal of I/O cells aligned along said second and fourth sides of said chip and said second bus line, said first and second interconnecting lines supplying power to the first and second bus lines and being aligned side-by-side and parallel to one another; a third interconnecting power line formed on a separate layer insulated from said first electrode layer and extending straight from said first bus line parallel to said first side of said chip, said third interconnecting power line crossing said basic cell row longitudinally; a fourth interconnecting ground line formed on the first electrode layer and extending straight from said second bus line parallel to said first side of said chip, said fourth interconnecting ground line crossing said basic cell row longitudinally, wherein said third and fourth interconnecting lines are aligned side-by-side and parallel to one another, and said basic cells are supplied from said third and fourth interconnecting lines, and wherein said first and second predetermined pitches are determined independently of each other.

Claim 4

A gate array arrangement formed on a rectangular chip having first, second, third, and fourth sides, in which the first and second sides are orthogonal to each other and third and fourth sides are respectively parallel to said first and second sides, said gate array arrangement comprising: a plurality of I/O cells aligned along four sides of said rectangular semiconductor chip with a first predetermined pitch, each I/O cell having a power source output terminal and a ground terminal for outputting voltage by an externally provided wire through an electric power pad, said terminals being located at identical positions in each of said I/O cells; a plurality of basic cells aligned in a plurality of rows extending in a space defined by said I/O cells, said rows being parallel to said first side of said chip and aligned with a second predetermined pitch; first and second bus lines formed on a first electrode layer, and both extending in parallel in a space between said I/O cells and said basic cells in a rectangular formation with four sides thereof being parallel to said four sides of said chip; a first interconnecting power line formed on a separate layer insulated from said first electrode layer and extending parallel to said first side of said chip and between said power source terminal of I/O cells aligned along said second and fourth sides of said chip and said first bus line; a second interconnecting ground line formed on a separate layer insulated from said first electrode layer, and extending parallel to said first side and said chip and between said ground terminal of I/O cells aligned along said second and fourth sides of said chip and said second bus line, said first and second interconnecting lines supplying power to the first and second bus lines and being aligned side-by-side and parallel to one another; a third interconnecting power line formed on a separate layer insulated from said first electrode layer and extending straight from said first bus line parallel to said first side of said chip, said third interconnecting power line crossing said basic cell row longitudinally; a fourth interconnecting ground line formed on the first electrode layer and extending straight from said second bus line parallel to said first side of said chip, said fourth interconnecting ground line crossing said basic cell row longitudinally, wherein said third and fourth interconnecting lines are aligned side-by-side and parallel to one another, and said basic cells are supplied from said third and fourth interconnecting lines, and wherein said first and second predetermined pitches are determined independently of each other.

Claim 5

A gate array arrangement as claimed in claim 2, wherein said first predetermined pitch is greater than said second predetermined pitch.

Claim 6

A gate array arrangement as claimed in claim 2, wherein said first predetermined pitch is smaller than said second predetermined pitch.

Claim 7

A gate array arrangement formed on a rectangular semiconductor chip having first, second, third and fourth sides, in which the first and second sides are orthogonal to each other and third and fourth sides are respectively parallel to said first and second sides, said gate array arrangement comprising: a plurality of I/O cells aligned along four sides of said rectangular semiconductor chip with a first predetermined pitch, each I/O cell having a power source terminal and a ground terminal, which terminals are located at identical positions in each of said I/O cells; a plurality of basic cells aligned in a plurality of rows extending in a space defined by said I/O cells, said rows being parallel to first side of said chip and aligned with a second predetermined pitch; first and second bus lines, both extending in a direction parallel to said second side of said chip and in a space between said I/O cells aligned along said second side of said chip and one opposite end of said basic cell rows and also in a space between said I/O cells aligned along said fourth side of said chip and an other opposite end of said basic cell rows; a first interconnecting power line extending parallel to said first side of said chip and between said power source terminal of I/O cells aligned along said second and fourth sides of said chip and first bus line; a second interconnecting ground line extending parallel to said first side of said chip and between said ground terminal of I/O cells aligned along said second and fourth sides of said chip and said second bus line wherein said first and second interconnecting lines are aligned side-by-side and parallel to one another; a third interconnecting power line extending straight from said first bus line parallel to said first side of said chip, said third interconnecting power line crossing said basic cell row longitudinally; a fourth interconnecting ground line extending straight from said second bus line parallel to said first side of said chip, said fourth interconnecting ground line crossing said basic cell row longitudinally, wherein said third and fourth interconnecting lines are aligned side-by-side and parallel one to another, and wherein said first and second predetermined pitches are determined independently of each other.

Claim 8

A gate array arrangement formed on a rectangular semiconductor chip having first, second, third and fourth sides, in which the first and second sides are orthogonal to each other and third and fourth sides are respectively parallel to said first and second sides, said gate array arrangement comprising: a plurality of I/O cells aligned along four sides of said rectangular semiconductor chip with a first predetermined pitch, each I/O cell having a power source terminal and a ground terminal, which terminals are located at identical positions in each of said I/O cells; a plurality of basic cells aligned in a plurality of rows extending in a space defined by said I/O cells, said rows being parallel to first side of said chip and aligned with a second predetermined pitch; first and second bus lines, both extending in a direction parallel to said second side of said chip and in a space between said I/O cells aligned along said second side of said chip and one opposite end of said basic cell rows and also in a space between said I/O cells aligned along said fourth side of said chip and an other opposite end of said basic cell rows; a first interconnecting power line extending parallel to said first side of said chip and between said power source terminal of I/O cells aligned along said second and fourth sides of said chip and first bus line; a second interconnecting ground line extending parallel to said first side of said chip and between said ground terminal of I/O cells aligned along said second and fourth sides of said chip and said second bus line wherein said first and second interconnecting lines are aligned side-by-side and parallel to one another; a third interconnecting power line extending straight from said first bus line parallel to said first side of said chip, said third interconnecting power line crossing said basic cell row longitudinally; a fourth interconnecting ground line extending straight from said second bus line parallel to said first side of said chip, said fourth interconnecting ground line crossing said basic cell row longitudinally, wherein said third and fourth interconnecting lines are aligned side-by-side and parallel one to another, and wherein said first and second predetermined pitches are determined independently of each other.

Claim 9

A gate array arrangement as claimed in claim 5, wherein said first predetermined pitch is greater than said second predetermined pitch.

Claim 10

A gate array arrangement as claimed in claim 5, wherein said first predetermined pitch is smaller than said second predetermined pitch.

Claim 11

A gate array arrangement formed on a rectangular semiconductor chip having first, second, third and fourth sides, in which the first and second sides are orthogonal to each other and third and fourth sides are respectively parallel to said first and second sides, said gate array arrangement comprising: a plurality of I/O cells aligned along four sides of said rectangular semiconductor chip with a first predetermined pitch, each I/O cell having a power source terminal and a ground terminal, which terminals are located at identical positions in each of said I/O cells; a plurality of basic cells aligned in a plurality of rows in a direction parallel to said first side with a third predetermined pitch; first and second bus lines, both extending in a space between said I/O cells and said basic cells in a rectangular formation with four sides thereof being parallel to said four sides of said chip; a first interconnecting power line extending parallel to said second side of said chip and between said power source terminal of I/O cells aligned along said first and third sides of said chip and said first bus line; a second interconnecting ground line extending parallel to said second side of said chip and between said ground terminal of I/O cells aligned along said first and third sides of said chip and said second bus line, wherein said first and second interconnecting lines are aligned side-by-side and parallel to one another; a third interconnecting power line extending straight from said first bus line parallel to said second side of said chip, said third interconnecting power line crossing said basic cell rows; a fourth interconnecting ground line extending straight from said second bus line parallel to said second side of said chip, said fourth interconnecting ground line crossing said basic cell rows, wherein said third and fourth interconnecting lines are aligned side-by-side and parallel to one another, and wherein said first and third predetermined pitches are determined independently of one another.

Claim 12

A gate array arrangement formed on a rectangular semiconductor chip having first, second, third and fourth sides, in which the first and second sides are orthogonal to each other and third and fourth sides are respectively parallel to said first and second sides, said gate array arrangement comprising: a plurality of I/O cells aligned along four sides of said rectangular semiconductor chip with a first predetermined pitch, each I/O cell having a power source terminal and a ground terminal, which terminals are located at identical positions in each of said I/O cells; a plurality of basic cells aligned in a plurality of rows in a direction parallel to said first side with a third predetermined pitch; first and second bus lines, both extending in a space between said I/O cells and said basic cells in a rectangular formation with four sides thereof being parallel to said four sides of said chip; a first interconnecting power line extending parallel to said second side of said chip and between said power source terminal of I/O cells aligned along said first and third sides of said chip and said first bus line; a second interconnecting ground line extending parallel to said second side of said chip and between said ground terminal of I/O cells aligned along said first and third sides of said chip and said second bus line, wherein said first and second interconnecting lines are aligned side-by-side and parallel to one another; a third interconnecting power line extending straight from said first bus line parallel to said second side of said chip, said third interconnecting power line crossing said basic cell rows; a fourth interconnecting ground line extending straight from said second bus line parallel to said second side of said chip, said fourth interconnecting ground line crossing said basic cell rows, wherein said third and fourth interconnecting lines are aligned side-by-side and parallel to one another, and wherein said first and third predetermined pitches are determined independently of one another.

Claim 13

A gate array arrangement as claimed in claim 8, wherein said third pitch is smaller than said first pitch.

Claim 14

A gate array arrangement as claimed in claim 8, wherein said rows are parallel to said first side of said chip and aligned with a second predetermined pitch.

Claim 15

A gate array arrangement as claimed in claim 10, further comprising: a fifth interconnecting power line (VDD) extending parallel to said first side of said chip and between said power source terminal of I/O cells aligned along said second and fourth sides of said chip and said first bus line; a sixth interconnecting ground line extending parallel to said first side of said chip and between said ground terminal of I/O cells aligned along said second and fourth sides of said chip and said second bus line; a seventh interconnecting power line extending from said first bus line parallelly to said first side of said chip, said seventh interconnecting power line crossing said basic cell row longitudinally; a eighth interconnecting ground line extending from said second bus line parallelly to said first side of said chip, said eighth interconnecting ground line crossing said basic cell row longitudinally, whereby said first and second predetermined pitches and are determined independently of each other.

Claim 16

A gate array arrangement formed on a rectangular semiconductor chip having first, second, third and fourth sides, in which the first and second sides are orthogonal to each other and third and fourth sides are respectively parallel to said first and second sides, said gate array arrangement comprising: a plurality of I/O cells aligned along four sides of said rectangular semiconductor chip with a first predetermined pitch, each I/O cell having a power source terminal and a ground terminal, which terminals are located at identical positions in each of said I/O cells; a plurality of basic cells aligned in a plurality of rows in a direction parallel to said first side with a third predetermined pitch; first and second bus lines, both extending in a direction parallel to said first side of said chip and in a space between said I/O cells aligned along said third side of said chip and said basic cell rows and also in a space between said I/O cells aligned along said first side of said chip and said basic cell rows; a first interconnecting power line extending parallel to said second side of said chip and between said power source terminal of I/O cells aligned along said first and third sides of said chip and said first bus line; a second interconnecting ground line extending parallel to said second side of said chip and between said ground terminal of I/O cells aligned along said first and third sides of said chip and said second bus line, wherein said first and second interconnecting lines are aligned side-by-side and parallel to one another; a third interconnecting power line extending straight from said first bus line parallel to said second side of said chip, said third interconnecting power line crossing said basic cell rows; a fourth interconnecting ground line extending straight from said second bus line parallel to said second side of said chip, said fourth interconnecting ground line crossing said basic cell rows, wherein said third and fourth interconnecting lines are aligned side-by-side and parallel to one another and wherein said first and third predetermined pitches are determined independently of one another.

Claim 17

A gate array arrangement formed on a rectangular semiconductor chip having first, second, third and fourth sides, in which the first and second sides are orthogonal to each other and third and fourth sides are respectively parallel to said first and second sides, said gate array arrangement comprising: a plurality of I/O cells aligned along four sides of said rectangular semiconductor chip with a first predetermined pitch, each I/O cell having a power source terminal and a ground terminal, which terminals are located at identical positions in each of said I/O cells; a plurality of basic cells aligned in a plurality of rows in a direction parallel to said first side with a third predetermined pitch; first and second bus lines, both extending in a direction parallel to said first side of said chip and in a space between said I/O cells aligned along said third side of said chip and said basic cell rows and also in a space between said I/O cells aligned along said first side of said chip and said basic cell rows; a first interconnecting power line extending parallel to said second side of said chip and between said power source terminal of I/O cells aligned along said first and third sides of said chip and said first bus line; a second interconnecting ground line extending parallel to said second side of said chip and between said ground terminal of I/O cells aligned along said first and third sides of said chip and said second bus line, wherein said first and second interconnecting lines are aligned side-by-side and parallel to one another; a third interconnecting power line extending straight from said first bus line parallel to said second side of said chip, said third interconnecting power line crossing said basic cell rows; a fourth interconnecting ground line extending straight from said second bus line parallel to said second side of said chip, said fourth interconnecting ground line crossing said basic cell rows, wherein said third and fourth interconnecting lines are aligned side-by-side and parallel to one another and wherein said first and third predetermined pitches are determined independently of one another.