Patent US4808850A successfully refreshed from Google Patents.
US4808850A
Expired / Lapsed
US
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Composite circuit of bipolar transistors and field effect transistors
Assignee: Hitachi Ltd
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Filing: 1987-01-02
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Granted: 1989-02-28
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Expires: 2007-01-02
Abstract
Abstract A novel composite circuit comprises a first bipolar transistor with a collector of a first conductivity type connected to a first potential, an emitter of the first conductivity type connected to an output, a second bipolar transistor with a collector of the first conductivity type connected to the output and an emitter of the first conductivity type connected to a second potential, a field effect transistor of a second conductivity type with a gate connected to an input, a source connected to a third potential and a drain connected to the base of the first bipolar transistor, a field effect transistor of the first conductivity type with a gate connected to the input, a drain connected to the base of the first bipolar transistor, and a source connected to the base of the second bipolar transistor, and a unidirectional element inserted between the output and the drain of the field effect transistor of the first conductivity type and having a direction of rectification opposite to that of the PN junction formed between the base and emitter of the first bipolar transistor.
Inventors
- 👤 Ikuro Masuda
- 👤 Masahiro Iwamura
- 👤 Motohisa Nishihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:06
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K19/01; H03K19/017
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
186 words
A NAND gate circuit comprising: a plurality of input terminals; an output terminal; a first bipolar transistor having its emitter-collector current path coupled between a first supply voltage terminal and said output terminal; a second bipolar transistor having its emitter-collector current path coupled between said output terminal and a second supply voltage terminal; a first plurality of MOS transistors, each having its drain-source current path coupled in parallel between said first supply voltage terminal and a base of said first bipolar transistor, each of said first plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; a second plurality of MOS transistors, each having its drain-source current path coupled in series between said output terminal and a base of said second bipolar transistor, each of said second plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; and a first MOS transistor having its drain-source current path coupled between said base of said second bipolar transistor and said second supply voltage terminal, and having a control electrode coupled to said output terminal.
Claim 2
Dependent Claim
186 words
A NAND gate circuit comprising: a plurality of input terminals; an output terminal; a first bipolar transistor having its emitter-collector current path coupled between a first supply voltage terminal and said output terminal; a second bipolar transistor having its emitter-collector current path coupled between said output terminal and a second supply voltage terminal; a first plurality of MOS transistors, each having its drain-source current path coupled in parallel between said first supply voltage terminal and a base of said first bipolar transistor, each of said first plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; a second plurality of MOS transistors, each having its drain-source current path coupled in series between said output terminal and a base of said second bipolar transistor, each of said second plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; and a first MOS transistor having its drain-source current path coupled between said base of said second bipolar transistor and said second supply voltage terminal, and having a control electrode coupled to said output terminal.
Claim 3
Dependent Claim
186 words
A NOR gate circuit comprising: a plurality of input terminals; an output terminal; a first bipolar transistor having its emitter-collector current path coupled between a first supply voltage terminal and said output terminal; a second bipolar transistor having its emitter-collector current path coupled between said output terminal and a second supply voltage terminal; a first plurality of MOS transistors, each having its drain-source current path coupled in series between said first supply voltage terminal and a base of said first bipolar transistor, each of said first plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; a second plurality of MOS transistors, each having its drain-source current path coupled in parallel between said output terminal and a base of said second bipolar transistor, each of said second plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; and a first MOS transistor having its drain-source current path coupled between said base of said second bipolar transistor and said second supply voltage terminal, and having a control electrode coupled to said output terminal.
Claim 4
Dependent Claim
186 words
A NOR gate circuit comprising: a plurality of input terminals; an output terminal; a first bipolar transistor having its emitter-collector current path coupled between a first supply voltage terminal and said output terminal; a second bipolar transistor having its emitter-collector current path coupled between said output terminal and a second supply voltage terminal; a first plurality of MOS transistors, each having its drain-source current path coupled in series between said first supply voltage terminal and a base of said first bipolar transistor, each of said first plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; a second plurality of MOS transistors, each having its drain-source current path coupled in parallel between said output terminal and a base of said second bipolar transistor, each of said second plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; and a first MOS transistor having its drain-source current path coupled between said base of said second bipolar transistor and said second supply voltage terminal, and having a control electrode coupled to said output terminal.
Claim 5
Dependent Claim
155 words
An inverter circuit comprising: an input terminal; an output terminal; a first bipolar transistor having its emitter-collector current path coupled between a first supply voltage terminal and said output terminal; a second bipolar transistor having its emitter-collector current path coupled between said output terminal and a second supply voltage terminal; a first MOS transistor having its drain-source current path coupled between said first supply voltage terminal and a base of said first bipolar transistor, said first MOS transistor having a control electrode coupled to said input terminal; a second MOS transistor having its drain-source current path coupled between said output terminal and a base of said second bipolar transistor, said second transistor having a control electrode coupled to said input terminal; and a MOS transistor having its drain-source current path coupled between said base of said second bipolar transistor and said second supply voltage terminal, and having a control electrode coupled to said output terminal.
Claim 6
Dependent Claim
155 words
An inverter circuit comprising: an input terminal; an output terminal; a first bipolar transistor having its emitter-collector current path coupled between a first supply voltage terminal and said output terminal; a second bipolar transistor having its emitter-collector current path coupled between said output terminal and a second supply voltage terminal; a first MOS transistor having its drain-source current path coupled between said first supply voltage terminal and a base of said first bipolar transistor, said first MOS transistor having a control electrode coupled to said input terminal; a second MOS transistor having its drain-source current path coupled between said output terminal and a base of said second bipolar transistor, said second transistor having a control electrode coupled to said input terminal; and a MOS transistor having its drain-source current path coupled between said base of said second bipolar transistor and said second supply voltage terminal, and having a control electrode coupled to said output terminal.
Claim 7
Dependent Claim
162 words
A gate circuit comprising: at least one input terminal; an output terminal; a first bipolar transistor having its emitter-collector current path coupled between a first supply voltage terminal and said output terminal; a second bipolar transistor having its emitter-collector current path coupled between said output terminal and a second supply voltage terminal; at least one first MOS transistor having its drain-source current path coupled between said first supply voltage terminal and a base of said first bipolar transistor, said first MOS transistor having a control electrode coupled to said input terminal; at least one second MOS transistor having its drain-source current path coupled between said output terminal and a base of said second bipolar transistor, said second MOS transistor having a control electrode coupled to said input terminal; and a MOS transistor having its drain-source current path coupled between said base of said second bipolar transistor and said second supply voltage terminal, and having a control electrode coupled to said output terminal.
Claim 8
Dependent Claim
162 words
A gate circuit comprising: at least one input terminal; an output terminal; a first bipolar transistor having its emitter-collector current path coupled between a first supply voltage terminal and said output terminal; a second bipolar transistor having its emitter-collector current path coupled between said output terminal and a second supply voltage terminal; at least one first MOS transistor having its drain-source current path coupled between said first supply voltage terminal and a base of said first bipolar transistor, said first MOS transistor having a control electrode coupled to said input terminal; at least one second MOS transistor having its drain-source current path coupled between said output terminal and a base of said second bipolar transistor, said second MOS transistor having a control electrode coupled to said input terminal; and a MOS transistor having its drain-source current path coupled between said base of said second bipolar transistor and said second supply voltage terminal, and having a control electrode coupled to said output terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-28 | 1992-08-29 | 1993-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-28 | 1996-08-29 | 1997-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-28 | 2000-08-29 | 2001-02-28 | $7700.00 | Window Closed / Lapsed |