US4808840A
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US
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Dynamic edge-triggered latch
Assignee: International Business Machines Corp
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Filing: 1987-11-20
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Granted: 1989-02-28
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Expires: 2007-11-20
Abstract
Abstract An edge-triggered latch is disclosed which has a low setup time and almost no metastability problem. It comprises a dynamic sensing means for detecting the voltage level of the data signal and at least one dynamic buffer for amplifying said detected voltage level into one of two logic levels recognizable by a static latch wherein the sampled result is stored.
Inventors
- 👤 Paul W. Chung
- 👤 Niantsu N. Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:55
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356026
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
84 words
An apparatus for producing an edge-triggered signal for use in an edge-triggered latch, comprising: dynamic sensing means responsive to a trigger signal and a data signal for detecting the voltage level of said data signal; means for producing a pulse delayed with respect to the trigger signal; dynamic buffer means coupled to said sensing means for amplifying said detected voltage level; and means responsive to said pulse for gating the amplified detected voltage signal into one of two logic levels recognizable by the latch.
Claim 2
Independent Claim
84 words
An apparatus for producing an edge-triggered signal for use in an edge-triggered latch, comprising: dynamic sensing means responsive to a trigger signal and a data signal for detecting the voltage level of said data signal; means for producing a pulse delayed with respect to the trigger signal; dynamic buffer means coupled to said sensing means for amplifying said detected voltage level; and means responsive to said pulse for gating the amplified detected voltage signal into one of two logic levels recognizable by the latch.
Claim 3
Dependent Claim
25 words
The apparatus as in claim 1, wherein said buffer comprises means for precharging said sensing means to reduce the setup time of the sensing means.
Claim 4
Dependent Claim
20 words
The apparatus as in claim 1, wherein said dynamic buffer means comprises at least one pair of cross-coupled FET devices.
Claim 5
Dependent Claim
18 words
The apparatus as in claim 1, wherein said sensing means comprises at least two FETS connected in series.
Claim 6
Dependent Claim
74 words
The apparatus as in claim 1, wherein there are two nodes, each node connected to said dynamic buffer means, and to a respective sensing means, said dynamic buffer means comprising means operative in one state to precharge and equalize the voltage level at said nodes for reducing switching time when said dynamic buffer means is operative in its other state to amplify said detected voltage level as detected by one of said sensing means.
Claim 7
Dependent Claim
84 words
An edge-triggered latch, comprising: a static latch; a dynamic sensing means responsive to a trigger signal and a data signal for detecting the voltage level of said data signal; dynamic buffer means coupled to said sensing means for amplifying said detected voltage level into one of two logic levels recognizable by said static latch; and gating means coupled to said static latch and said dynamic buffer means for gating the output of said dynamic buffer means to said static latch between predetermined time windows.
Claim 8
Dependent Claim
84 words
An edge-triggered latch, comprising: a static latch; a dynamic sensing means responsive to a trigger signal and a data signal for detecting the voltage level of said data signal; dynamic buffer means coupled to said sensing means for amplifying said detected voltage level into one of two logic levels recognizable by said static latch; and gating means coupled to said static latch and said dynamic buffer means for gating the output of said dynamic buffer means to said static latch between predetermined time windows.
Claim 9
Dependent Claim
29 words
An edge-triggered latch as in claim 6, further comprising mean for precharging and equalizing said sensing means to reduce the setup time between the trigger signal and data signal.
Claim 10
Dependent Claim
28 words
An edge-triggered latch as in claim 6 wherein said dynamic buffer means comprises a pair of cross-coupled p-channel FET devices and a pair of cross-coupled n-channel FET devices.
Claim 11
Dependent Claim
24 words
An edge-triggered latch as in claim 6, wherein said sensing means comprises at least two FETs of the same channel type connected in series.
Claim 12
Independent Claim
71 words
A method of producing an edge-triggered signal from a data signal and a trigger signal, said edge-triggered signal to be stored by an edge-triggered latch, comprising the steps of: detecting the voltage level of said data signal using a dynamic sensing device; and using a dynamic buffer means, amplifying said detected voltage level; and gating the amplified detected voltage level into one of two logic levels recognizable by said static latch.
Claim 13
Independent Claim
71 words
A method of producing an edge-triggered signal from a data signal and a trigger signal, said edge-triggered signal to be stored by an edge-triggered latch, comprising the steps of: detecting the voltage level of said data signal using a dynamic sensing device; and using a dynamic buffer means, amplifying said detected voltage level; and gating the amplified detected voltage level into one of two logic levels recognizable by said static latch.
Claim 14
Dependent Claim
38 words
The method as in claim 10, comprising the further steps of precharging and equalizing the voltage level at two nodes connected to the dynamic sensing device to reduce the setup time between the trigger signal and data signal.
Claim 15
Dependent Claim
20 words
The method as in claim 10, wherein said dynamic buffer means comprises at least one pair of cross-coupled FET devices.
Claim 16
Dependent Claim
23 words
The method as in claim 10, wherein said sensing device comprises at least two FETs of the same channel type connected in series.
Claim 17
Dependent Claim
47 words
The method as in claim 11, wherein during the amplifying step, the voltage level at one node is detected and amplified relative to that of the other node, and during said gating step, the voltages at both nodes are gated to the static latch as differential inputs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1992-02-28 | 1992-08-29 | 1993-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-28 | 1996-08-29 | 1997-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-28 | 2000-08-29 | 2001-02-28 | $7700.00 | Window Closed / Lapsed |