Patent US4808546A successfully refreshed from Google Patents.
US4808546A
Expired / Lapsed
US
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SOI process for forming a thin film transistor using solid phase epitaxy
Assignee: Hitachi Ltd
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Filing: 1987-02-02
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Granted: 1989-02-28
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Expires: 2007-02-02
Abstract
Abstract Of an amorphous Si film, a region to be formed into a lowly doped region such as the channel region of an MOS transistor is covered with a mask and an uncovered region is doped with an impurity. After this, the amorphous Si film is annealed and turned to signal crystal through solid phase epitaxial growth, and the mask itself is used as the electrode of a semiconductor device. By this impurity doping, a large-sized single-crystal Si film can be formed, and the impurity doping can be conducted in self-alignment with the electrode formation to produce a highly integrated semiconductor circuit.
Inventors
- 👤 Masahiro Moniwa
- 👤 Masanobu Miyao
- 👤 Shoji Shukuri
- 👤 Eiichi Murakami
- 👤 Terunori Warabisako
- 👤 Masao Tamura
- 👤 Nobuyoshi Natsuaki
- 👤 Kiyonori Ohyu
- 👤 Tadashi Suzuki
- 👤 Yuuichi Madokoro
- 👤 Yasuo Wada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 07:59
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/38; H10P14/3802; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10P14/22; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/2926; H10P14/32; H10P14/3202; H10P14/3238; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/3451; H10P14/3452; H10P14/3458; H10P14/3466; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1912; H10W; H10W10/00; H10W10/10; H10W10/181; Y; Y10; Y10S; Y10S148/00; Y10S148/003; Y10S148/048; Y10S148/09; Y10S148/154
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
161 words
A process for fabricating a semiconductor device, comprising: the step of forming an insulating film having apertures on the principal surface of a single-crystal semiconductor substrate; the step of forming an amorphous semiconductor film extending from the exposed surface of said semiconductor substrate onto said insulating film; the step of forming a mask on such regions of said amorphous semiconductor film as will have a low impurity concentration, said mask constituting an electrode of said semiconductor device; the step of doping those regions of said amorphous semiconductor film, which are not covered with said mask, with an impurity, the regions that are doped forming impurity-doped regions of the semiconductor device; and the step of annealing said amorphous semiconductor film to form the doped portions of said amorphous semiconductor film into single-crystal semiconductor films through the solid-phase epitaxial growth while electrically activating the impurity atoms, so as to simultaneously provide the single-crystal semiconductor films and the impurity-doped regions of the semiconductor device.
Claim 2
Dependent Claim
161 words
A process for fabricating a semiconductor device, comprising: the step of forming an insulating film having apertures on the principal surface of a single-crystal semiconductor substrate; the step of forming an amorphous semiconductor film extending from the exposed surface of said semiconductor substrate onto said insulating film; the step of forming a mask on such regions of said amorphous semiconductor film as will have a low impurity concentration, said mask constituting an electrode of said semiconductor device; the step of doping those regions of said amorphous semiconductor film, which are not covered with said mask, with an impurity, the regions that are doped forming impurity-doped regions of the semiconductor device; and the step of annealing said amorphous semiconductor film to form the doped portions of said amorphous semiconductor film into single-crystal semiconductor films through the solid-phase epitaxial growth while electrically activating the impurity atoms, so as to simultaneously provide the single-crystal semiconductor films and the impurity-doped regions of the semiconductor device.
Claim 3
Dependent Claim
30 words
A semiconductor device fabricating process according to claim 1, wherein said single-crystal semiconductor substrate and said amorphous semiconductor film are a single-crystal Si substrate and an amorphous Si film respectively.
Claim 4
Dependent Claim
25 words
A semiconductor device fabricating process according to claim 1, wherein said annealing step is conducted at a temperature ranging from 400° C. to 800° C.
Claim 5
Dependent Claim
23 words
A semiconductor device fabricating process according to claim 1, wherein said impurity is selected from a group consisting of phosphorus, arsenic and boron.
Claim 6
Dependent Claim
21 words
A semiconductor device fabricating process according to claim 1, wherein said impurity is implanted substantially up to its solid solubility limit.
Claim 7
Dependent Claim
29 words
A semiconductor device fabricating process according to claim 1, wherein the regions of said single-crystal semiconductor film covered with said mask provide the channel regions of an MOS transistor.
Claim 8
Dependent Claim
31 words
A semiconductor device fabricating process according to claim 1, wherein the regions of said single-crystal semiconductor film doped with said impurity provide the source and drain regions of an MOS transistor.
Claim 9
Dependent Claim
27 words
A semiconductor device fabricating process according to claim 1, the region of said single-crystal semiconductor film covered with said mask provides the base of a bipolar transistor.
Claim 10
Dependent Claim
25 words
A semiconductor device fabricating process according to claim 1, wherein the regions doped with said impurity provide the emitter and collector of a bipolar transistor.
Claim 11
Dependent Claim
20 words
A semiconductor device fabricating process according to claim 1, wherein said electrode is the gate electrode of an MOS transistor.
Claim 12
Dependent Claim
20 words
A semiconductor device fabricating process according to claim 1, wherein said electrode is the base electrode of a bipolar transistor.
Claim 13
Dependent Claim
33 words
A semiconductor device fabricating process according to claim 1, wherein said amorphous semiconductor film is formed extending from directly in contact with the exposed surface of said semiconductor surface onto said insulating film.
Claim 14
Dependent Claim
59 words
A semiconductor device fabricating process according to claim 1, wherein the semiconductor device is formed in an active region of the single-crystal semiconductor films, and wherein the doping and annealing are performed so as to promote the growth of the single-crystal semiconductor films through solid-phase epitaxial growth and to provide doped portions which constitute part of the semiconductor device.
Claim 15
Dependent Claim
43 words
A semiconductor device fabricating process according to claim 13, wherein said doping is performed so as to introduce the impurity in self-alignment with said mask, whereby, in said semiconductor device, the impurity-doped regions of the semiconductor device are in self-alignment with said electrode.
Claim 16
Dependent Claim
28 words
A semiconductor device fabricating process according to claim 1, wherein said insulating film is formed so as to be coplanar with the exposed surface of the semiconductor substrate.
Claim 17
Dependent Claim
24 words
A semiconductor device fabricating process according to claim 1, wherein a single amorphous semiconductor film is formed between said insulating film and said mask.
Claim 18
Dependent Claim
34 words
A semiconductor device fabricating process according to claim 16, wherein said single amorphous semiconductor film is formed extending from directly in contact with the exposed surface of said semiconductor surface onto said insulating film.
Claim 19
Dependent Claim
48 words
A semiconductor device fabricating process according to claim 1, wherein the step of annealing causes the regions of the amorphous semiconductor film covered with said mask to be single-crystallized so as to form the regions of the amorphous semiconductor film covered with said mask into single-crystal semiconductor films.
Claim 20
Dependent Claim
39 words
A semiconductor device fabricating process according to claim 1, wherein the mask is provided over the insulating film, and regions of the amorphous semiconductor film having a low impurity concentration are formed in direct contact with the insulating film.
Claim 21
Dependent Claim
39 words
A semiconductor device fabricating process according to claim 13, wherein the mask is provided over the insulating film, and regions of the amorphous semiconductor film having a low impurity concentration are formed in direct contact with the insulating film.
Claim 22
Dependent Claim
19 words
A semiconductor device fabricating process according to claim 1, wherein said amorphous semiconductor film is a single semiconductor film.
Claim 23
Dependent Claim
63 words
A semiconductor device fabricating process according to claim 21, wherein, after the step of doping and annealing, the single semiconductor film has first portions, that extend between opposed surfaces thereof furthest from and closest to the substrate, that have a low impurity concentration; and second portions, that extend between said opposed surfaces, different from said first portions, that have a high impurity concentration.
Claim 24
Dependent Claim
27 words
A semiconductor device fabricating process according to claim 22, wherein said single semiconductor film is formed in direct contact with the exposed surface of the semiconductor substrate.
Claim 25
Dependent Claim
32 words
A semiconductor device fabricating method according to claim 1, wherein said mask is formed on regions of the amorphous semiconductor film that will have a low impurity concentration in said semiconductor device.
References Cited (Backward Citations)
US4113533A
Cited
US4499657A
Cited
US4609407A
Cited
US4487639A
Cited
US4494300A
Cited
US4468855A
Cited
US4498951A
Cited
US4557036A
Cited
US4643777A
Cited
US4628588A
Cited
US4654958A
Cited
JPH11169A
Cited
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