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US4807119A
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Memory address mapping mechanism
Assignee: Toshiba Corp
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Filing: 1986-07-24
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Granted: 1989-02-21
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Expires: 2006-07-24
Abstract
Abstract A memory address mapping mechanism includes a flip-flop for latching a signal (PROT) representing the real or protective virtual address mode. AN output signal from the flip-flop is supplied to an address decoder. In either the real or protective virtual address mode, the address decoder receives the address signal from a microprocessor and the signal (PROT) from the flip-flop, decodes the address signal so as to obtain a continuous memory address space, and outputs a memory address selection signal.
Inventors
- 👤 Masao Suga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:23
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
169 words
A memory address mapping mechanism in a computer system comprising a microprocessor and a memory system, the microprocessor generating address signals and an address mode signal, and having at least two address modes whose address spaces have different sizes, wherein each of the address spaces is divided into at least two sub-spaces, each having a specified, preliminarily-fixed use, the memory system having predetermined locations selected in response to memory address selection signals, the memory address mapping mechanism comprising: address mode-selecting means for latching the address mode signal from the microprocessor; and address decoding means connected to the address mode-selecting means for receiving the address signals from the microprocessor and the address mode signal from the address mode-selecting means, for decoding the address signals in accordance with the address mode signal, for producing memory address selection signals from the decoded address signals to specify a logical continuous-address space consisting of at least two sub-spaces having the same use, and for outputting the memory address selection signals to the memory system.
Claim 2
Dependent Claim
169 words
A memory address mapping mechanism in a computer system comprising a microprocessor and a memory system, the microprocessor generating address signals and an address mode signal, and having at least two address modes whose address spaces have different sizes, wherein each of the address spaces is divided into at least two sub-spaces, each having a specified, preliminarily-fixed use, the memory system having predetermined locations selected in response to memory address selection signals, the memory address mapping mechanism comprising: address mode-selecting means for latching the address mode signal from the microprocessor; and address decoding means connected to the address mode-selecting means for receiving the address signals from the microprocessor and the address mode signal from the address mode-selecting means, for decoding the address signals in accordance with the address mode signal, for producing memory address selection signals from the decoded address signals to specify a logical continuous-address space consisting of at least two sub-spaces having the same use, and for outputting the memory address selection signals to the memory system.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-21 | 1992-08-22 | 1993-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-21 | 1996-08-22 | 1997-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-21 | 2000-08-22 | 2001-02-21 | $7700.00 | Window Closed / Lapsed |