US4432053A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Address generating apparatus and method
Assignee: Unisys Corp
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Filing: 1981-06-29
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Granted: 1984-02-14
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Expires: 2001-06-29
Abstract
Abstract Address generating apparatus which uses narrow data paths for generating a wide logical address and which also provides for programs to access very large shared data structures outside their normally available addressing range. Selective indexed addressing is employed for providing both index data and variable dimension override data. During address generation, selected index data is used in conjunction with a displacement provided by an instruction for determining an offset. Dimension override data accompanying the selected index data is used to selectively access an address locating entry in a table of entries corresponding to the applicable program. The resulting accessed address locating entry is in turn used to determine the particular portion of memory against which the offset is to be applied.
Inventors
- 👤 Blaine D. Gaither
- 👤 William W. Farley, IV
- 👤 Albert Johnson
- 👤 Brian L. Parker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:47
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/342; G06F2212/00; G06F2212/65; G06F2212/656
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
222 words
In a data processing system having a memory and an address translator, improved apparatus for generating a logical address for use by said translator in accessing said memory, said apparatus comprising: means for storing data indicative of a logical address, said data including index selection data and displacement data; a plurality of index registers each including index data and address override data; means responsive to said index selection data for selecting one of said index registers; a logical address register having first and second portions; means including an adder for adding the index data in a selected index register to said displacement data and for storing the result in said first portion of said logical address register; table storing means for storing a plurality of tables each containing a plurality of address locating entries for a corresponding one of a plurality of programs performable by said system; selection means responsive to a program identification signal provided by said system and to said address data in a selected index register for accessing a corresponding one of the address locating entries in a selected one of said tables and for storing this accessed entry in said second portion of said logical address register; and means for applying the contents of the first and second portions of said logical address register to said address translator.
Claim 2
Dependent Claim
222 words
In a data processing system having a memory and an address translator, improved apparatus for generating a logical address for use by said translator in accessing said memory, said apparatus comprising: means for storing data indicative of a logical address, said data including index selection data and displacement data; a plurality of index registers each including index data and address override data; means responsive to said index selection data for selecting one of said index registers; a logical address register having first and second portions; means including an adder for adding the index data in a selected index register to said displacement data and for storing the result in said first portion of said logical address register; table storing means for storing a plurality of tables each containing a plurality of address locating entries for a corresponding one of a plurality of programs performable by said system; selection means responsive to a program identification signal provided by said system and to said address data in a selected index register for accessing a corresponding one of the address locating entries in a selected one of said tables and for storing this accessed entry in said second portion of said logical address register; and means for applying the contents of the first and second portions of said logical address register to said address translator.
Claim 3
Dependent Claim
41 words
The invention in accordance with claim 1, wherein said means for storing data indicative of a logical address is an instruction register additionally containing operation data indicating a type of operation to be performed on data located at said logical address.
Claim 4
Dependent Claim
49 words
The invention in accordance with claim 1 or 2, wherein said index register also includes sign data, and wherein said adder means is responsive to said sign data for determining whether the index data in a selected index register is to be added to or subtracted from said displacement.
Claim 5
Dependent Claim
36 words
The invention in accordance with claim 1 or 2, wherein said memory includes a plurality of segments, and wherein each data locating entry in a table is indicative of the base address of a particular segment.
Claim 6
Dependent Claim
55 words
the invention in accordance with claim 4, wherein a table corresponding to a program includes address locating entries corresponding to the base addresses of segments assigned to the program, and wherein the table also includes at least one address locating entry corresponding to the base address of a segment which is shared with another program.
Claim 7
Dependent Claim
19 words
The invention in accordance with claim 5, wherein each address locating entry includes check data indicating the status thereof.
Claim 8
Dependent Claim
37 words
The invention in accordance with claim 4, wherein the sum of said displacement and the index data in a selected index register determines the resultant location accessed in the segment indicated by the selected address locating entry.
Claim 9
Dependent Claim
70 words
The invention in accordance with claim 7, wherein overflow detecting means are provided for detecting when the sum of said displacement and the index data in a selected index register designates a location which is outside of the segment whose base address is indicated by a selected address locating entry, and means responsive to said overflow detecting means to said system for taking corrective action when an overflow is detected.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-13 | 1987-08-15 | 1988-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-13 | 1991-08-15 | 1992-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-13 | 1995-08-15 | 1996-02-14 | $7700.00 | Window Closed / Lapsed |