Patent US4806846A successfully refreshed from Google Patents.
US4806846A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High accuracy direct reading capacitance-to-voltage converter
Assignee: Individual
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Filing: 1987-07-06
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Granted: 1989-02-21
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Expires: 2007-07-06
Abstract
Abstract A relatively simple circuit for implementing a low-cost, low power, highly accurate capacitance-to-voltage converter by which to measure the unknown capacitance of a capacitor. The circuit is characterized by the ability to eliminate error due to stray capacitance sources. The circuit is implemented by a crystal controlled clock generator which produces multi-phase clock signals to control the operation of a pair of series connected field effect transistors and a buffer amplifier. The field effect transistors are alternately switched on and off to periodically charge and discharge the capacitor under measurement between a source of reference potential and the inverting input terminal of a precision operational amplifier. The output voltage of the operational amplifier tracks the capacitance of the capacitor under measurement, such that an accurate indication of its capacitance is obtained by merely reading the output of the operational amplifier.
Inventors
- 👤 George L. Kerber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:42
CPC Classifications
G; G01; G01R; G01R27/00; G01R27/02; G01R27/26; G01R27/2605
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
165 words
A circuit for providing an accurate measurement of the capacitance of a capacitor, said circuit comprising: clock signal generator means for providing a signal which alternates between relatively high and low signal levels, said signal generator means interconnected with a first plate of said capacitor to supply said clock signal thereto; operatonal amplifier means having first input terminal means connected to a summing node, second input terminal measn connected to ground, and output terminal means providing an output voltage signal, said capacitor being discharged into said summing node at the first input terminal means of said operational amplifier means; and means for successively charging and discharging said capacitor as said clock signal alternates between relatively high and low signal levels, said charging and discharging means including switch means connected between the second plate of said capacitor and said summing node; the magnitude of the voltage signal at the output terminal means of said operational amplifier means providing a measurement of the capacitance of said capacitor.
Claim 2
Dependent Claim
165 words
A circuit for providing an accurate measurement of the capacitance of a capacitor, said circuit comprising: clock signal generator means for providing a signal which alternates between relatively high and low signal levels, said signal generator means interconnected with a first plate of said capacitor to supply said clock signal thereto; operatonal amplifier means having first input terminal means connected to a summing node, second input terminal measn connected to ground, and output terminal means providing an output voltage signal, said capacitor being discharged into said summing node at the first input terminal means of said operational amplifier means; and means for successively charging and discharging said capacitor as said clock signal alternates between relatively high and low signal levels, said charging and discharging means including switch means connected between the second plate of said capacitor and said summing node; the magnitude of the voltage signal at the output terminal means of said operational amplifier means providing a measurement of the capacitance of said capacitor.
Claim 3
Dependent Claim
83 words
The circuit recited in claim 1, wherein said means for charging and discharging said capacitor also includes a buffer amplifier connected between said clock signal generator means to receive said clock signal therefrom and the first plate of said capacitor for charging said capacitor each time that said clock signal is at the relatively high signal level, the closure of said switch means discharging said capacitor into said summing node each time that said clock signal is at the relatively low signal level.
Claim 4
Dependent Claim
45 words
The circuit recited in claim 1, further comprising a charge catching capacitor connected to the first input terminal means of said operational amplifier means to reduce the amplitude of switch transients from said switch means and thereby prevent the saturation of said operational amplifier means.
Claim 5
Dependent Claim
44 words
The circuit recited in claim 1, wherein said switch means includes at least one multi-terminal semiconductor device having a conduction path connected between the second plate of said capacitor and said summing node at the first input terminal means of said operational amplifier means.
Claim 6
Dependent Claim
27 words
The circuit recited in claim 4, wherein said multi-terminal semiconductor device is a field effect transistor having a pair of conduction path terminals and a control terminal.
Claim 7
Dependent Claim
40 words
The circuit recited in claim 5, wherein said switch means comprises a pair of said field effect transistors having their respective conduction paths connected in electrical series between the first input terminal means of said operational amplifier means and ground.
Claim 8
Dependent Claim
31 words
The circuit recited in claim 6, wherein said clock signal generator means is connected to the respective control terminals of said pair of field effect transistors to control the operations thereof.
Claim 9
Dependent Claim
16 words
The circuit recited in claim 7, wherein said clock signal generator means supplies multi-phase clock signals.
Claim 10
Dependent Claim
55 words
The circuit recited in claim 6, wherein said clock signal generator means applies non-overlapping multi-phase clock signals to the respective control terminsla of said pair of field effect transistors, such that one of said transistors is rendered conducting while the other transistor is rendered non-conducting, and vice versa, for successively charging and discharging said capacitor.
Claim 11
Dependent Claim
17 words
The circuit recited in claim 1, wherein said clock signal generator means includes a crystal controlled oscillator.
Claim 12
Dependent Claim
30 words
THe circuit recited in claim 1, further comprising an RC low pass filter connected between the output terminal means and the first input terminal means of said operational amplifier means.
Claim 13
Dependent Claim
43 words
The circuit recited in claim 1, further comprising a resistor connected between a source of reference potential and the first input terminal means of said operational amplifier means to provide for offset compensation of the output terminal means of said operational amplifier means.
Claim 14
Dependent Claim
144 words
A capacitance-to-voltage converter circuit for providing an accurate measurement of the capacitance of a capacitor, said circuit comprising: clock means for supplying a clock signal which alternates between relatively high and relatively low voltage levels; operational amplifier means having input and output terminal means; and means for successively charging and discharging said capacitor including a buffer amplifier interconnected between said clock means and one plate of said capacitor for charging said capacitor during a first portion of the clock signal, and multi-terminal semiconductor switch means interconnected between said operational amplifier means and the second plate of said capacitor for discharging said capacitor to the input terminal means of said operational amplifier means during a second portion of the clock signal; the magnitude of the voltage at the output terminal means of said operational amplifier means providing a measurement of the capacitance of said capacitor.
Claim 15
Dependent Claim
144 words
A capacitance-to-voltage converter circuit for providing an accurate measurement of the capacitance of a capacitor, said circuit comprising: clock means for supplying a clock signal which alternates between relatively high and relatively low voltage levels; operational amplifier means having input and output terminal means; and means for successively charging and discharging said capacitor including a buffer amplifier interconnected between said clock means and one plate of said capacitor for charging said capacitor during a first portion of the clock signal, and multi-terminal semiconductor switch means interconnected between said operational amplifier means and the second plate of said capacitor for discharging said capacitor to the input terminal means of said operational amplifier means during a second portion of the clock signal; the magnitude of the voltage at the output terminal means of said operational amplifier means providing a measurement of the capacitance of said capacitor.
Claim 16
Dependent Claim
15 words
The circuit recited in claim 13, wherein said clock means includes a crystal controlled oscillator.
Claim 17
Dependent Claim
27 words
The circuit recited in claim 14, wherein said clock means also includes a non-overlapping clock generator which is driven by the output of said crystal controlled oscillator.
Claim 18
Dependent Claim
39 words
The circuit recited in claim 13, wherein the input terminal means of said operational amplifier means comprises an inverting input terminal connected to said semiconductor switch means at a virtual ground and a non-inverting input terminal connected to ground.
Claim 19
Dependent Claim
81 words
The circuit recited in claim 16, wherein said semiconductor switch means comprises a pair of field effect transistors having their respective conduction paths connected in electrical series between the inverting input terminal of said operational amplifier means and ground, said clock means being connected to the respective control terminals of said pair of field effect transistors to control the operation thereof, and the second plate of said capacitor being connected to the series node between said pair of field effect transistors.
Claim 20
Dependent Claim
53 words
The circuit recited in claim 17, wherein said clock means also applies non-overlapping clock signals to the respective control terminals of said pair of field effect transistors, such that one of said transistors is rendered conducting while the other transistor is rendered non-conducting, and vice versa, for successively charging and discharging said capacitor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-21 | 1992-08-22 | 1993-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-21 | 1996-08-22 | 1997-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-21 | 2000-08-22 | 2001-02-21 | $7700.00 | Window Closed / Lapsed |