TTL-to-ECL input translator/driver circuit

Claim 2

A high speed low power voltage translation circuit for translating input signals that vary between relatively large first and second positive voltages into output signals that vary between relatively small third and fourth negative voltage levels comprising: means for providing a first positive voltage threshold reference having a value between said first and second voltages; a circuit node; means, responsive to the input signals, for generating an intermediate voltage at said circuit node, said intermediate voltage being positive and having a relatively small voltage swing; a self-centering reference translator means for translating said first positive voltage threshold reference into a second voltage threshold having a value between said third and fourth voltage levels; and buffer driver means responsive to the voltages at said circuit node and to said second voltage threshold for generating said output signals.

Claim 3

The circuit recited in claim 1 wherein said circuit includes a constant current source and said means for generating an intermediate voltage at said circuit node comprises first, second and third transistors, a diode and a resistor, the collectors and the emitters of said transistors being connected together, the bases of said transistors being connected by said diode, the base of said first transistor being connected to said TTL input, the emitters of said transistors being connected to said constant source, whereby depending on the value of the signal at said input, current passes through either said first or said second transistors.

Claim 4

The circuit recited in claim 1 wherein said self-centering reference translator means includes first and second transistors and first and second resistors, said resistors being connected in series from said first reference to said second reference, said first transistor having its collector connected to said first reference, its emitter connected to the second reference and its base connected to the midpoint of said resistors, said second transistor having both its emitter and its base connected to said first reference and its base connected to said second reference.

Claim 5

The circuit recited in claim 1 wherein said buffer driver means comprises, first, second and third resistors, and first, second and third transistors, connected to form an ECL current switch, a first side of said switch being connected to said ECL reference and the second side of said switch being connected to said circuit node through a level shifter.

Claim 6

A high speed low power voltage translation circuit for translating TTL input signals that vary between nominal values of 0.4 volts and 3.5 volts into ECL signals that vary between nominal values of -1500 millivolts and -800 millivolts comprising: means for providing a first positive voltage threshold reference having a value equal to two transistor base-emitter junction voltages; a circuit node; a TTL input comparator having first and second transistors, a Schottky diode and a constant current source, the base of said first transistor being connected to receive said input signal via said Schottky diode, and the base of said second transistor being connected to said reference voltage, the emitter of said transistors being connected to said circuit node, said constant current source connected to draw current from either said first or said second transistor depending up whether said input signal is higher or lower than said first positive voltage threshold, whereby an intermediate positive voltage is generated at said circuit node, said intermediate voltage changing between 1.16 volts and 1.92 volts in response to changes in said TTL input signal; a self-centering reference translator means for translating said first positive voltage threshold reference into a negative ECL voltage threshold which tracks said first voltage threshold reference; and buffer driver means responsive to the voltages at said circuit node and to said second voltage threshold for generating said ECL output signals.

Claim 7

A high speed low power voltage translation circuit for translating TTL input signals that vary between nominal values of 0.4 volts and 3.5 volts into ECL signals that vary between nominal values of -1500 millivolts and -800 millivolts comprising: means for providing a first positive voltage threshold reference having a value equal to two transistor base-emitter junction voltages; a circuit node; a TTL input comparator having first and second transistors, a Schottky diode and a constant current source, the base of said first transistor being connected to receive said input signal via said Schottky diode, and the base of said second transistor being connected to said reference voltage, the emitter of said transistors being connected to said circuit node, said constant current source connected to draw current from either said first or said second transistor depending up whether said input signal is higher or lower than said first positive voltage threshold, whereby an intermediate positive voltage is generated at said circuit node, said intermediate voltage changing between 1.16 volts and 1.92 volts in response to changes in said TTL input signal; a self-centering reference translator means for translating said first positive voltage threshold reference into a negative ECL voltage threshold which tracks said first voltage threshold reference; and buffer driver means responsive to the voltages at said circuit node and to said second voltage threshold for generating said ECL output signals.

Claim 8

A high speed low power circuit for translating TTL input voltages into ECL output voltages comprising: circuit means for generating a TTL input reference signal; a circuit node; an input clamped level shifting comparator for comparing said TTL voltages to said TTL input reference signal and for generating an intermediate voltage signal at said circuit node; a self-centering reference threshold translator means for translating said TTL reference signal to an ECL reference signal; an ECL buffer driver responsive to signals at said circuit node and to said ECL reference signal for generating said ECL output voltages.

Claim 9

A high speed low power circuit for translating TTL input voltages into ECL output voltages comprising: circuit means for generating a TTL input reference signal; a circuit node; an input clamped level shifting comparator for comparing said TTL voltages to said TTL input reference signal and for generating an intermediate voltage signal at said circuit node; a self-centering reference threshold translator means for translating said TTL reference signal to an ECL reference signal; an ECL buffer driver responsive to signals at said circuit node and to said ECL reference signal for generating said ECL output voltages.

Claim 10

The circuit recited in claim 6 wherein said circuit means for generating a TTL input reference signal comprises, a resistor, first and second transistors and a diode connected in series, each transistor having a base and a collector, a connection between the base and the collector of each of said transistors, said resistor being connected to the emitter of said first transistor, the emitter of the first transistor being connected to the collector of said second transistor, said diode being connected to the emitter of said second transistor.