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US4805085A Expired / Lapsed US ⏱️ 0.0 years remaining

Digital control system for electronic apparatus

Assignee: Sony Corp
•
Filing: 1988-06-06
•
Granted: 1989-02-14
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Expires: 2008-06-06
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Abstract

Abstract A digital control system for electronic apparatus employs an internal bus system and includes at least one master controller and a plurality of operational circuits connected via control bus lines so that, during normal operation of the electronic apparatus, the master controller can carry out predetermined control operations relative to the respective circuit blocks. During testing and/or adjustment, an auxiliary master control circuit is connected to the control bus lines in order to control the operational circuitry in place of the master control circuit, while holding the master control in the slave mode.

Inventors

  • 👤 Takao Mogi
  • 👤 Masayuki Suematsu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 05:29
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/042; G05B19/0421

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 274 words
A digital control system for use in electronic apparatus, comprising: master control means arranged within the electronic apparatus containing first operational dat and producing a data signal and a clock signal; a plurality of operational circuit elements arranged within the electronic apparatus and connected to be controlled by said master control means; control bus lines comprising a data signal line and a clock signal line interconnecting said master control means and said plurality of operational cirucit elements, said control bus lines being in a release state upon occurence of a predetermined relationship between said clock signal and data signal; said master control means including means for declaring itself master master of said electronic apparatus upon occurence of said predetermined relationship and an inhibit register for inhibiting said master control means from declaring itself the master and placing said master control means in a slave mode upon receipt of a predetermined data word; and auxiliary master control means arranged external to the electronic apparatus and adapted to be connected to said control bus lines and transmitting second operational data by way of said control bus lines for alternatively controlling said operational circuit elements in place of said master control means and in which said second operational data in said auxiliary master control measn includes said predetermined data word for placing said master control means in said slave mode by transmitting said selected data word to said inhibit register in said master control means by way of said control bus lines, and in which said master control means includes means for returning to a master mode a predetermined time after being placed into the slave mode.
Claim 2
Dependent Claim 274 words
A digital control system for use in electronic apparatus, comprising: master control means arranged within the electronic apparatus containing first operational dat and producing a data signal and a clock signal; a plurality of operational circuit elements arranged within the electronic apparatus and connected to be controlled by said master control means; control bus lines comprising a data signal line and a clock signal line interconnecting said master control means and said plurality of operational cirucit elements, said control bus lines being in a release state upon occurence of a predetermined relationship between said clock signal and data signal; said master control means including means for declaring itself master master of said electronic apparatus upon occurence of said predetermined relationship and an inhibit register for inhibiting said master control means from declaring itself the master and placing said master control means in a slave mode upon receipt of a predetermined data word; and auxiliary master control means arranged external to the electronic apparatus and adapted to be connected to said control bus lines and transmitting second operational data by way of said control bus lines for alternatively controlling said operational circuit elements in place of said master control means and in which said second operational data in said auxiliary master control measn includes said predetermined data word for placing said master control means in said slave mode by transmitting said selected data word to said inhibit register in said master control means by way of said control bus lines, and in which said master control means includes means for returning to a master mode a predetermined time after being placed into the slave mode.
Claim 3
Dependent Claim 46 words
A digital control system according to claim 1, further comprising a connector terminal connected to said control bus lines and adapted to be connected to said externally arranged auxiliary master control means, whereby said auxiliary master control means is temporarily connected to said control bus lines.
Claim 4
Dependent Claim 42 words
A digital control system according to claim 2, in which said auxiliary control means includes means for transmitting address data specifying the master control means to receive control data in advance of a change in operational mode of said master control means.
Claim 5
Dependent Claim 40 words
A digital control system according to claim 1, in which said auxiliary control means includes means for transmitting address data specifying the master control means to receive control data prior to changing an operational mode of said master control means.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-02-14 1992-08-15 1993-02-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-02-14 1996-08-15 1997-02-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-02-14 2000-08-15 2001-02-14 $7700.00 Window Closed / Lapsed

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