EP0051332A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Two-wire bus-system comprising a clock wire and a data wire for interconnecting a number of stations
Assignee: Koninklijke Philips NV
•
Filing: 1981-10-22
•
Granted: —
•
Expires: 2001-10-22
Abstract
Abstract A computer system comprises a number of stations which are interconnected by means of a clock bus wire (20) and a data bus wire (22) which both form a wired logic function of the signals generated thereon by the stations (32, 34). During the clock pulses, the signal on the data bus wire is stationary; it may change between the clock pulses. Start and stop conditions are formed by a signal combination between clock bus wire and data bus wire (60 and 62, respectively) which is not permissible in a data stream. If there is more than one master station so that a composite clock signal occurs on the clock bus wire, the clocks of the relevant master stations are each time resynchronized to the actual transitions in the composite clock signal.
Inventors
- 👤 Adrianus Peter Martin M. Moelands
- 👤 Herman Schutte
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 12:51
CPC Classifications
H; H04; H04L; H04L12/00; G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4282; G06F13/4291; H04L7/00; H04L7/0008; G06F2213/00; G06F2213/0016
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
337 words
A computer system, comprising a first number of stations (32, 34) which are interconnected by a two-wire line, comprising a clock wire (20) and a data wire (22) for transporting thereon a series of data bits, and per data bit a synchronizing clock signal in parallel therewith, between at least one transmitting station and at least one receiving station, characterized in that said clock wire is a clock bus wire and said data wire is a data bus wire, both wires being provided with means (28, 30) for forming a wired logic function between the voltage levels which denote a first and a second logic value respectively which are transmitted by the relevant stations, so that the voltage level on both wires can be pulled to the first logic value by each station connected, said set of transmitting/receiving stations comprising master stations and slave stations, each master station comprising first means for generating a clock pulse having the second logic value. on the clock wire per bit cell, said at least one transmitting station comprising second means for presenting a data bit on the data wire per bit cell for a period of time which covers the duration of the associated clock pulse on the clock pulse wire, including the edges thereof, each master station also comprising: a) third means for forming a first stop signal by forming a signal transition on the data wire from said first to said second logic value, during the presence of a signal of the second logic value on the clock wire; b) fourth means for forming a first start signal by forming a signal transition on the data wire from said second logic value to said first logic value during the presence of a signal of the second logic value on the clock wire; all non-master stations connected comprising fifth means for continuously presenting said second logic value to the clock wire, all non-transmitting stations connected comprising sixth means for continuously presenting said second logic value to the data wire.
Claim 2
Dependent Claim
337 words
A computer system, comprising a first number of stations (32, 34) which are interconnected by a two-wire line, comprising a clock wire (20) and a data wire (22) for transporting thereon a series of data bits, and per data bit a synchronizing clock signal in parallel therewith, between at least one transmitting station and at least one receiving station, characterized in that said clock wire is a clock bus wire and said data wire is a data bus wire, both wires being provided with means (28, 30) for forming a wired logic function between the voltage levels which denote a first and a second logic value respectively which are transmitted by the relevant stations, so that the voltage level on both wires can be pulled to the first logic value by each station connected, said set of transmitting/receiving stations comprising master stations and slave stations, each master station comprising first means for generating a clock pulse having the second logic value. on the clock wire per bit cell, said at least one transmitting station comprising second means for presenting a data bit on the data wire per bit cell for a period of time which covers the duration of the associated clock pulse on the clock pulse wire, including the edges thereof, each master station also comprising: a) third means for forming a first stop signal by forming a signal transition on the data wire from said first to said second logic value, during the presence of a signal of the second logic value on the clock wire; b) fourth means for forming a first start signal by forming a signal transition on the data wire from said second logic value to said first logic value during the presence of a signal of the second logic value on the clock wire; all non-master stations connected comprising fifth means for continuously presenting said second logic value to the clock wire, all non-transmitting stations connected comprising sixth means for continuously presenting said second logic value to the data wire.
Claim 3
Dependent Claim
121 words
2 . A communication system as claimed in Claim 1, characterized in that in the case of at least two simultaneously transmitting stations, these stations are all master stations, each master station comprising a time slot generator (108, 110) with an input for receiving a second start signal (78, 86) which is generated on the clock wire and for supplying an "end" signal (114) after termination of the time slot started thereby, said first means being suitable for forming a modified signal (76, 83, 84) for the clock wire under the control of said "end" signal, there also being provided a detector (116) for detecting a signal transition on the clock wire as an exclusive representation of said second start signal.
Claim 4
Dependent Claim
78 words
A station for use as a master station in a communication system as claimed in Claim 1 wherein said second and fourth means are suitable for starting a data transport operation by successively forming: said first start signal; a first series of at least two data bits having said first logic value; a second series of at least one data bit having said second logic value; a third start signal whose shape corresponds to the first start signal;
Claim 5
Dependent Claim
36 words
A communication system for use with a station as claimed in Claim 3, wherein all stations connected comprise an interrogation device, whose "dead"time is shorter than the value corresponding to the length of said first series.
References Cited (Backward Citations)
US3889236A
Cited
EP0008416A1
Cited
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.