US4803665A
Expired / Lapsed
US
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Signal transition detection circuit
Assignee: Fujitsu Ltd
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Filing: 1987-08-07
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Granted: 1989-02-07
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Expires: 2007-08-07
Abstract
Abstract A signal transition detection circuit comprises a decoder circuit (1) for decoding a plurality of signals, a delay circuit (2) having a rise delay time period (T r ) and a fall time period (T f ) which are different from each other, and a logic circuit (3). The logic circuit performs a logic operation upon the outputs of the delay circuit to generate a pulse signal (ATD) for indicating at least one transition of the signals.
Inventors
- 👤 Yasushi Kasa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:01
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/18; H; H03; H03K; H03K5/00; H03K5/153; H03K5/1534
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
156 words
A signal transition detection circuit comprising: decoder means for decoding a plurality of signals to generate decoding signals; delay means, connected to said decoder circuit and having plural outputs, for delaying the decoding signals, said delay means having a rise delay time period and a fall delay time period which are different from each other; and wherein each or said delay means comprise a plurality of delay circuits, each including: a first capacitor connected to said decoder means; two serially-connected inverters connected to said first capacitor and having an output, each of said serially-connected inverters having a rise time period and a fall time period which are different from each other; and a second capacitor connected to the output of said serially connected inverters; logic means, connected to said delay means, for performing a logic operation upon the outputs of said delay means to generate a pulse signal indicating a transition of said plurality of signals.
Claim 2
Dependent Claim
156 words
A signal transition detection circuit comprising: decoder means for decoding a plurality of signals to generate decoding signals; delay means, connected to said decoder circuit and having plural outputs, for delaying the decoding signals, said delay means having a rise delay time period and a fall delay time period which are different from each other; and wherein each or said delay means comprise a plurality of delay circuits, each including: a first capacitor connected to said decoder means; two serially-connected inverters connected to said first capacitor and having an output, each of said serially-connected inverters having a rise time period and a fall time period which are different from each other; and a second capacitor connected to the output of said serially connected inverters; logic means, connected to said delay means, for performing a logic operation upon the outputs of said delay means to generate a pulse signal indicating a transition of said plurality of signals.
Claim 3
Dependent Claim
18 words
A circuit as set forth in claim 1, wherein said delay means is incorporated into said decoder means.
Claim 4
Dependent Claim
185 words
A semiconductor memory device comprising: memory means having a plurality of memory cells; decoder means, connected to said memory means, for receiving address signals to generate decoding signals, thereby selecting one memory cell from said memory means; delay means, connected to said decoder means and having plural outputs, for delaying said decoding signals with a rise time period and a fall time period which are different form each other; wherein said delay means comprises a plurality of delay circuits, each including: a first capacitor connected to said decoder means; two serially-connected inverters connected to said first capacitor and having an output, each of said serially-connected inverters having a rise time period and a fall time period which are different from each other; and a second capacitor connected to an outputs of said serially connected inverters. logic means, connected to said delay means, for performing a logic operation upon the outputs of said delay means to generate an address transition detection signal; and reset means, connected to said logic means and to said memory means, for resetting said memory means by said address transition detection signal.
Claim 5
Dependent Claim
185 words
A semiconductor memory device comprising: memory means having a plurality of memory cells; decoder means, connected to said memory means, for receiving address signals to generate decoding signals, thereby selecting one memory cell from said memory means; delay means, connected to said decoder means and having plural outputs, for delaying said decoding signals with a rise time period and a fall time period which are different form each other; wherein said delay means comprises a plurality of delay circuits, each including: a first capacitor connected to said decoder means; two serially-connected inverters connected to said first capacitor and having an output, each of said serially-connected inverters having a rise time period and a fall time period which are different from each other; and a second capacitor connected to an outputs of said serially connected inverters. logic means, connected to said delay means, for performing a logic operation upon the outputs of said delay means to generate an address transition detection signal; and reset means, connected to said logic means and to said memory means, for resetting said memory means by said address transition detection signal.
Claim 6
Dependent Claim
18 words
A device as set forth in claim 3, wherein said delay means is incorporated into said decoder means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-07 | 1992-08-08 | 1993-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-07 | 1996-08-08 | 1997-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-07 | 2000-08-08 | 2001-02-07 | $7700.00 | Window Closed / Lapsed |