Packet bus interface

Claim 1

An arbitrated bus interface circuit for use in a system including a bus and an external processor, said arbitrated bus interface comprising: an arbitrated bus port connected to said bus and operated to acknowledge receipt of data from said bus; said arbitrated bus port comprising; address recognition means connected to said bus and operated to decode mini packets and accept those having a predetermined address bit pattern; frame timing means connected to said bus and operated to detect a sync signal in each mini packet and provide a corresponding timing signal; flow control means connected to said bus and operable to provide busy and packet transferred signals; a first custom buffer interface connected to a custom buffer circuit and said flow control means and operable to detect the availability of mini packets from an outbound buffer space in said custom buffer circuit; and a command processor interface connected to said custom buffer circuit and operated to store parameter information associated with each mini packet; a receiver-transmitter port connected to said external processor and operable to interrupt said external processor; said receiver-transmitter port comprises: a second custom buffer interface operated to transfer data to and from the custom buffer circuit; an external processor interface connected to said second custom buffer interface and operated to transfer data to and from said external processor; and control means connected to said second custom buffer interface and said external processor interface and operated to control the transfer of mini packets between the second custom buffer interface and the external microprocessor interface; a custom buffer circuit comprising inbound and outbound shift registers and connected between said arbitrated bus port and said receiver-transmitter port and operated to store data received from and transmitted to said arbitrated bus port and said receiver-transmitter port, and further operated to provide an interrupt enable signal in response to storing a predetermined amount of data, said receiver transmitter port operated in response to said interrupt enable signal to interrupt said external processor; and a command processor connected to said arbitrated bus port, said receiver-transmitter port and said custom buffer circuit, and operated to arbitrate on said bus.