Sense amplifier circuit for semiconductor memory

Claim 1

A sense amplifier circuit comprising: first amplifier means for detecting data from a memory cell and generating an output signal in accordance with the detected data; a first load MOS transistor of one conductivity type connected between an output terminal of said first amplifier means and a power source terminal; second amplifier means for detecting data from a dummy cell and generating an output signal in accordance with the detected data; a second load MOS transistor of one conductivity type and a third load MOS transistor which is an enhancement type N-channel MOS transistor whose gate and drain are connected to said power source terminal, said second load MOS transistor and said third load MOS transistor being connected in parallel between an output terminal of said second amplifier means and said power source terminal, a back gate of said third load MOS transistor being connected to a reference potential terminal; comparing means for comparing the output signals from said first and second amplifier means and generating an output signal in accordance with the result of the comparison; bias voltage generating means for generating a bias output voltage, wherein said first amplifier means has a first N-channel MOS transistor with first and second ends, said first end being connected to said comparing means, and a second N-channel MOS transistor connected between the second end of said first N-channel MOS transistor and said power source terminal; wherein said second amplifier means has a third N-channel MOS transistor with first and second ends, said first end being connected to said comparing means, and a fourth N-channel MOS transistor connected between the second end of said third N-channel MOS transistor and said power source terminal; and wherein said output voltage of said bias voltage generating means is applied to gates of said first to fourth N-channel MOS transistors.