Computer memory refresh circuit

Claim 2

In a computer including a central processing unit, display means for displaying display data, and memory means having a plurality of addressable storage locations forming a first memory area used for data processing effected in said central processing unit and a second memory area for storing display data to be displayed on said display means, the improvement comprising: changeover switch means having first, second and third input terminals and an output terminal, the latter connected to an address input terminal of said memory means; display address signal generating means for generating display address signals corresponding to storage locations of said second memory area of said memory means and for outputting said address signals to said first input terminal of said changeover switch means; refresh address signal generating means for generating refresh address signals corresponding to storage locations of said second memory area of said memory means and for outputting said refresh address signals to said second input terminal of said changeover switch means; an address bus, connected to said central processing unit, and being operatively connected to said third input terminal of said changeover switch means, for supplying address signals corresponding to storage locations of said first memory area of said memory means; display signal detecting means for detecting display data read out of the second memory area of said memory means; and switching control means for controlling said changeover switch means so that: (a) the address signal input terminal of said memory means is connected to an output terminal of said display address signal generating means via said first input terminal of said changeover switch means when said display signal detecting means detects display data being read out of said second memory area of said memory means, and (b) when said display signal detecting means detects no display data being read out of said second memory area of said memory means the address signal input terminal of said memory means is connected to the output terminal of said refresh address signal generating means, via said second input terminal of said changeover switch, for a predetermined time period at predetermined intervals during a display frame time, and the address signal input terminal of said memory means is connected to said address bus, via said third input terminal of said changeover switch means, during a remaining portion of said display frame time.

Claim 3

The improvement according to claim 1, wherein said changeover switch means comprises: first switch means connected to both said display address signal generating means and said refresh address signal generating means for selectively transmitting either display address signals from said display address signal generating means or refresh address signals from said refresh address signal generating means; and second switch means connected to both an output terminal of said first switch means and said address bus for supplying either one of the signals being transmitted from said first switch means and the address signal supplied through said address bus to the address signal input terminal of said memory means.

Claim 4

The improvement according to claim 2, wherein said changeover switch means operates such that: when said display signal detecting means detects no display data, said second switch is controlled by said switching control means to connect said address bus to the address signal input terminal of said memory means, and both said first and second switches are controlled to connect the output terminal of said refresh address signal generating means to the address signal input terminal of said memory means for a predetermined time period at predetermined intervals.

Claim 5

The improvement according to claim 1, wherein said display signal detecting means includes means for detecting the presence or absence of reading of display data in synchronous relation with a vertical synchronizing signal for controlling said display means.

Claim 6

The improvement according to claim 1, wherein detecting of the presence or absence of display data by said display signal detecting means occurs once within a period of a single field.

Claim 7

The improvement according to claim 1, wherein said refresh address signal generating means comprises a refresh counter providing burst mode refresh during said predetermined time period.

Claim 8

In a computer including a central processing unit, display means for displaying display data, and memory means having a plurality of addressable storage locations forming a first memory area used for data processing effected in said central processing unit and a second memory area for storing display data to be displayed on said display means, the improvement comprising: changeover switch means, having first, second and third input terminals and an output terminal the latter connected to an address input terminal of said memory means; display address signal generating means for generating display address signals corresponding to storage locations of said second memory area of said memory means and for outputting said address signals to said first input terminal of said changeover switch means; refresh address signal generating means for generating refresh address signals corresponding to storage locations of said second area of said memory means and for outputting said refresh address signals to said second input terminal of said changeover switch means; an address bus, connected to said central processing unit, and being operatively connected to said third input terminal of said changeover switch means for supplying address signals corresponding to storage locations of said first memory area of said memory means and display command signals indicating whether or not data in said memory means is being displayed on the display means; display command signal detecting means for detecting display data read out of the second memory area of said memory means in response to the presence of a display command signal at a display control means; and switching control means for controlling said changeover switch means so that: (a) the address signal input terminal of said memory means is connected to an output terminal of said display address signal generating means via said first input terminal of said changeover switch means when said display command signal detecting means detects display data being read out of said second memory area of said memory means in response to a display command signal received at said display control means, and (b) when said display command signal detecting means detects no display data being read out of said second memory area of said memory means in response to the absence of a display command signal, the address signal input terminal of said memory means is connected to the output terminal of said refresh address signal generating means, via said second input terminal of said changeover switch means, for a predetermined time period at predetermined intervals during a display frame time, and the address signal input terminal of said memory means is connected to said address bus, via said third input terminal of said changeover switch means, during a remaining portion of said display frame time.

Claim 9

In a computer including a central processing unit, display means for displaying display data, and memory means having a plurality of addressable storage locations forming a first memory area used for data processing effected in said central processing unit and a second memory area for storing display data to be displayed on said display means, the improvement comprising: changeover switch means, having first, second and third input terminals and an output terminal the latter connected to an address input terminal of said memory means; display address signal generating means for generating display address signals corresponding to storage locations of said second memory area of said memory means and for outputting said address signals to said first input terminal of said changeover switch means; refresh address signal generating means for generating refresh address signals corresponding to storage locations of said second area of said memory means and for outputting said refresh address signals to said second input terminal of said changeover switch means; an address bus, connected to said central processing unit, and being operatively connected to said third input terminal of said changeover switch means for supplying address signals corresponding to storage locations of said first memory area of said memory means and display command signals indicating whether or not data in said memory means is being displayed on the display means; display command signal detecting means for detecting display data read out of the second memory area of said memory means in response to the presence of a display command signal at a display control means; and switching control means for controlling said changeover switch means so that: (a) the address signal input terminal of said memory means is connected to an output terminal of said display address signal generating means via said first input terminal of said changeover switch means when said display command signal detecting means detects display data being read out of said second memory area of said memory means in response to a display command signal received at said display control means, and (b) when said display command signal detecting means detects no display data being read out of said second memory area of said memory means in response to the absence of a display command signal, the address signal input terminal of said memory means is connected to the output terminal of said refresh address signal generating means, via said second input terminal of said changeover switch means, for a predetermined time period at predetermined intervals during a display frame time, and the address signal input terminal of said memory means is connected to said address bus, via said third input terminal of said changeover switch means, during a remaining portion of said display frame time.

Claim 10

The improvement according to claim 1, wherein said memory means comprises a dynamic random access memory.

Claim 11

The improvement according to claim 7, wherein said memory means comprises a dynamic random access memory.