Adjustable delay element for digital systems

Claim 2

An adjustable delay circuit for delaying passage of a digital signal, comprising: low-pass filter means for passing the lower frequency component of the digital signal, the lower frequency component having a delay relative to the digital signal; high-pass filter means in parallel with the low-pass filter means for passing the higher frequency component of the digital signal; control means for coupling a selectable portion of the higher frequency component to be summed with the lower frequency component to vary the delay produced by the lower frequency component; and an output stage for receiving the lower frequency component and selected portion of the of the higher frequency component to reproduce the digital signal with the corresponding delay.

Claim 3

The delay circuit of claim 1 in which the control means comprises a current multiplier that couples the high frequency component to the lower frequency component with which the higher frequency component is in phase in response to a control signal.

Claim 4

The delay circuit of claim 1 in which the low-pass filter means comprises a resistor and stray capacitance within the circuit and the high-pass filter means comprises a capacitor adapted to pass the higher frequency component filtered by the low-pass filter means.

Claim 5

The adjustable delay circuit of claim 1 in which the control means is adapted to provide a delay in the digital signal symmetrical with respect to the positive-going and negative-going transitions thereof.

Claim 6

A variable delay circuit for delaying passage of a digital signal, comprising: an input stage for producing a pair of oppositely phased differential output voltage signals representing the digital signal; a pair of low-pass filters each receiving one of the output voltage signals from the input stage for passing the lower frequency component of the output voltage signals, each lower frequency component having a delay relative to the output voltage signal; a current multiplier comprising two pairs of emitter-coupled transitors, the collector of one transistor of each pair coupled directly to the output of one low-pass filter and the collector of the other transistor of each pair cross coupled to the output of the other low-pass filter, the bases of the directly coupled transistor tied together and the bases of the cross-coupled transistors tied together; a pair of high-pass filters each having an input and an output, each input receiving one of the output voltage signals from the input stage and each output being respectively coupled to the emitters of each pair of emitter-coupled transistors; means for providing a pair of differential currents, one to the bases of the directly coupled transistors and one to the bases of the cross-coupled transistors, to couple a selectable portion of the higher frequency component from each high-pass filter to be summed with the lower frequency component from each low-pass filter to vary the delay within the output voltage signals; and an output stage comprising a comparator for comparing output voltage signals, each including the lower frequency component and the selectable portion of the higher frequency component, and reproducing the digital signal with corresponding delay as one output voltage signals exceeds the other and causes the comparator to change state.

Claim 7

A variable delay circuit for delaying passage of a digital signal, comprising: an input stage for producing a pair of oppositely phased differential output voltage signals representing the digital signal; a pair of low-pass filters each receiving one of the output voltage signals from the input stage for passing the lower frequency component of the output voltage signals, each lower frequency component having a delay relative to the output voltage signal; a current multiplier comprising two pairs of emitter-coupled transitors, the collector of one transistor of each pair coupled directly to the output of one low-pass filter and the collector of the other transistor of each pair cross coupled to the output of the other low-pass filter, the bases of the directly coupled transistor tied together and the bases of the cross-coupled transistors tied together; a pair of high-pass filters each having an input and an output, each input receiving one of the output voltage signals from the input stage and each output being respectively coupled to the emitters of each pair of emitter-coupled transistors; means for providing a pair of differential currents, one to the bases of the directly coupled transistors and one to the bases of the cross-coupled transistors, to couple a selectable portion of the higher frequency component from each high-pass filter to be summed with the lower frequency component from each low-pass filter to vary the delay within the output voltage signals; and an output stage comprising a comparator for comparing output voltage signals, each including the lower frequency component and the selectable portion of the higher frequency component, and reproducing the digital signal with corresponding delay as one output voltage signals exceeds the other and causes the comparator to change state.

Claim 8

An adjustable delay circuit from delaying passage of a digital signal, comprising: an emitter follower for receiving the digital signal; a low-pass filter coupled to the emitter of the emitter follower for passing the lower frequency component of the digital signal to introduce a delay into the signal; a high-pass filter coupled to the emitter of the emitter follower in parallel with the low-pass filter for passing the high frequency component of the digital signal; control means for biasing the emitter follower with a constant current and for coupling a selectable portion of the high frequency component to be summed with the lower frequency component; and an output stage for receiving the lower frequency component and selected portion of the higher frequency component to reproduce the digital signal with the delay.

Claim 9

An adjustable delay circuit from delaying passage of a digital signal, comprising: an emitter follower for receiving the digital signal; a low-pass filter coupled to the emitter of the emitter follower for passing the lower frequency component of the digital signal to introduce a delay into the signal; a high-pass filter coupled to the emitter of the emitter follower in parallel with the low-pass filter for passing the high frequency component of the digital signal; control means for biasing the emitter follower with a constant current and for coupling a selectable portion of the high frequency component to be summed with the lower frequency component; and an output stage for receiving the lower frequency component and selected portion of the higher frequency component to reproduce the digital signal with the delay.