Binary logic circuits utilizing diverse frequency representation for bits

Claim 1

A HIGH FREQUENCY LOGICAL ELEMENT COMPRISING, A FIRST AND A SECOND SOURCE OF ELECTRICAL SIGNALS, EACH OF SAID ELECTRICAL SIGNALS HAVING ONE OF FREQUENCIES F1 AND F2, A FIRST HYBRID JUNCTION HAVING TWO PAIRS OF CONJUGATE ARMS, MEANS CONNECTING SAID FIRST SOURCE OF ELECTRICAL SIGNALS TO ONE ARM OF THE FIRST CONJUGATE PAIR OF ARMS OF SAID HYBRID JUNCTION, A FIRST AND A SECOND FILTER EACH CONNECTED TO A DIFFERENT ARM OF THE SECOND CONJUGATE PAIR OF ARMS OF SAID FIRST HYBRID JUNCTION, EACH OF SAID FILTERS ADAPTED TO PASS A DIFFERENT ONE OF SAID FREQUENCIES, A FIRST MIXER CONNECTED TO ONE OF SAID FILTERS FOR PRODUCING AN ELECTRICAL SIGNAL HAVING A FREQUENCY F3 EQUAL TO THE SUM OF SAID FREQUENCIES F1 AND F2, A SECOND HYBRID JUNCTION HAVING TWO PAIRS OF CONJUGATE ARMS, MEANS CONNECTING SAID FIRST MIXER TO ONE ARM OF THE FIRST CONJUGATE PAIR OF ARMS OF SAID SECOND HYBRID JUNCTION, A SECOND AND A THIRD MIXER EACH CONNECTED TO A DIFFERENT ARM OF THE SECOND CONJUGATE PAIR OF ARMS OF SAID SECOND HYBRID JUNCTION, SAID SECOND MIXER RESPONSIVE TO THE SIGNAL FROM SAID FIRST MIXER AND TO SIGNALS FROM SAID SECOND SOURCE OF SIGNALS FOR PRODUCING SIGNALS HAVING A FREQUENCY EQUAL TO THE DIFFERENCE BETWEEN FREQUENCY F3 AND ONE OF FREQUENCIES F1 AND F2, SAID THIRD MIXER RESPONSIVE TO THE SIGNALS FROM SAID FIRST AND SECOND MIXERS FOR PRODUCING SIGNALS HAVING ONE OF FREQUENCIES F1 AND F2, A DELAY ELEMENT HAVING A FIRST AND A SECOND TERMINAL, MEANS CONNECTING THE OTHER OF SAID FILTERS TO THE FIRST TERMINAL OF SAID DELAY ELEMENT, A THIRD HYBRID JUNCTION HAVING TWO PAIRS OF CONJUGATE ARMS, MEANS CONNECTING SAID THIRD MIXER AND THE SECOND TERMINAL OF SAID DELAY ELEMENT EACH TO A DIFFERENT ARM OF THE FIRST PAIR OF CONJUGATE ARMS OF SAID THIRD HYBRID JUNCTION, AN OUTPUT TERMINAL, AND MEANS CONNECTING SAID OUTPUT TERMINAL TO ONE ARM OF THE SECOND PAIR OF CONJUGATE ARMS OF SAID THIRD HYBRID JUNCTION.