Patent US4799040A successfully refreshed from Google Patents.
US4799040A
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Data conversion circuit
Assignee: Toshiba Corp
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Filing: 1987-01-30
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Granted: 1989-01-17
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Expires: 2007-01-30
Abstract
Abstract A data conversion circuit is constructed in such a manner that a plurality of flip-flop series, each including tandem connected master/slave flip-flops, are provided and driven by plural phase numbers of clock signals which have no overlap therebetween, so that a parallel data is obtained with a serial data supplied to the flip-flop series, or a serial data is obtained with a parallel data supplied to the flip-flop series. The clock signals employed here have no overlap between each of the corresponding phases of the signals.
Inventors
- 👤 Hisao Yanagi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:22
CPC Classifications
H; H03; H03M; H03M9/00; G; G11; G11C; G11C19/00; G11C19/28; G11C19/38; H03K; H03K5/00; H03K5/15; H03K5/151; H03K5/1515
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
179 words
A data conversion circuit for performing conversion between serial and parallel data comprising: a plurality of flip-flop series having master/slave flip-flops, the number of said master/slave flip-flops equal to the number of bits of said parallel data, said flip-flops having terminals for serial data and parallel data, respectively, and said flip-flops being divided into predetermined plural numbers of groups to respectively form said plurality of flip-flop series; and a clock signal generator circuit for generating clock signals, the phase number of said clock signals equal to the number of said plurality of flip-flop series and the respective phases of said clock signals not overlapping each other in phase, said clock signal generator circuit rendering to operate at the leading edge of said clock signals a master flip-flop and a slave flip-flop of the master/slave flip-flop contained in each of said flip-flop series, and also rendering said flip-flop series to operate in synchronization with each other; in which said flip-flop series are made operative upon said clock signals thereby to perform a data conversion between said serial and parallel data.
Claim 2
Dependent Claim
179 words
A data conversion circuit for performing conversion between serial and parallel data comprising: a plurality of flip-flop series having master/slave flip-flops, the number of said master/slave flip-flops equal to the number of bits of said parallel data, said flip-flops having terminals for serial data and parallel data, respectively, and said flip-flops being divided into predetermined plural numbers of groups to respectively form said plurality of flip-flop series; and a clock signal generator circuit for generating clock signals, the phase number of said clock signals equal to the number of said plurality of flip-flop series and the respective phases of said clock signals not overlapping each other in phase, said clock signal generator circuit rendering to operate at the leading edge of said clock signals a master flip-flop and a slave flip-flop of the master/slave flip-flop contained in each of said flip-flop series, and also rendering said flip-flop series to operate in synchronization with each other; in which said flip-flop series are made operative upon said clock signals thereby to perform a data conversion between said serial and parallel data.
Claim 3
Dependent Claim
58 words
A data conversion circuit according to claim 1, in which said flip-flop series each has an input terminal for said serial data, an output terminal for said parallel data, and an input terminal for respective ones of said clock signals; and in which said serial data supplied to said input terminal therefor is converted into said parallel data.
Claim 4
Dependent Claim
66 words
A data conversion circuit according to claim 2, in which said flip-flop series each have first and second master/slave flip-flops connected tandem with respect to each other, and said first master/slave flip-flop of each of said flip-flop series is provided with said serial data as its input; whereby said parallel data are respectively derived from the output terminals of said first and second master slave flip-flops.
Claim 5
Dependent Claim
197 words
A data conversion circuit for converting a parallel data input into a serial data output comprising: a plurality of flip-flop series having master/slave flip-flops, the number of which master/slave flip-flops equal to the number of bits of said parallel data, said flip-flops each having terminals for said serial data and parallel data, respectively, and said flip-flops being divided into predetermined plural numbers of groups to respectively form said plurality of flip-flop series; in which each of the master/slave flip-flops of each of said flip-flop series has an input terminal for said parallel data; a clock signal generator circuit for generating clock signals the phase number of which is equal to the number of said plurality of flip-flop series and the respective phases of said clock signals not overlapping each other in phase, said clock signal generator circuit rendering to operate at the leading edge of said clock signals a master flip-flop and a slave flip-flop of the master/slave flip-flop contained in each of said flip-flop series, and also rendering said flip-flop series to operate in synchronization with each other; and a selector circuit for selecting an output of each of said flip-flops and forming said serial data.
Claim 6
Dependent Claim
197 words
A data conversion circuit for converting a parallel data input into a serial data output comprising: a plurality of flip-flop series having master/slave flip-flops, the number of which master/slave flip-flops equal to the number of bits of said parallel data, said flip-flops each having terminals for said serial data and parallel data, respectively, and said flip-flops being divided into predetermined plural numbers of groups to respectively form said plurality of flip-flop series; in which each of the master/slave flip-flops of each of said flip-flop series has an input terminal for said parallel data; a clock signal generator circuit for generating clock signals the phase number of which is equal to the number of said plurality of flip-flop series and the respective phases of said clock signals not overlapping each other in phase, said clock signal generator circuit rendering to operate at the leading edge of said clock signals a master flip-flop and a slave flip-flop of the master/slave flip-flop contained in each of said flip-flop series, and also rendering said flip-flop series to operate in synchronization with each other; and a selector circuit for selecting an output of each of said flip-flops and forming said serial data.
Claim 7
Dependent Claim
80 words
The data conversion circuit for converting a parallel data input into a serial data output according to claim 4, in which said flip-flop series each have first and second master/slave flip-flops connected in tandem with respect to each other, and said parallel data input is supplied to said first and second master/slave flip-flops; whereby the output data from said second master/slave flip-flop of each of said flip-flop series is selectively derived therefrom in order to obtain said serial data output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-17 | 1992-07-18 | 1993-01-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-17 | 1996-07-18 | 1997-01-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-17 | 2000-07-18 | 2001-01-17 | $7700.00 | Window Closed / Lapsed |