Apparatus and method for connecting between series and parallel data streams

Claim 2

A charge transfer device shift register comprising 2M (M is an integer greater than one) parallel intermediate shift registers eacH register having an input node to receive an input data stream and an output node to provide an output data stream, and conversion means for applying data from an input data stream to the register input nodes, wherein the improvement comprises: charge transfer device input means included in the conversion means and connected as an M-level input logic tree, and means included in the conversion means for providing shift control of the charge transfer device input means thereby successively dividing alternate bits of data from the input data stream between two data streams until there are 2M data streams each stream being applied to a different register input node, the shift control having a different repetition rate at different levels of the input logic tree.

Claim 3

Apparatus as recited in claim 1 wherein the charge transfer device input means for dividing the data from a first input data stream flowing in a first input path between a second input data stream flowing in a second input path and a third input data stream flowing in a third input path comprises: a first charge transfer device storage cell having a shift terminal, an input node connected to the first input path and an output node connected to the second input path, a second charge transfer device storage cell having a shift terminal, an input node connected to the first input path and an output node connected to the third input path, and shift means connected to the shift terminals for producing a shift signal to repetitively make the first charge transfer device storage cell conducting while the second charge transfer device storage cell is nonconducting, and to repetitively make the second charge transfer device storage cell conducting while the first charge transfer device storage cell is nonconducting.

Claim 4

Apparatus as recited in claim 2 wherein the shift means comprises means to halve the repetition rate of the shift signal applied to charge transfer device storage cells at each successive level of the input logic tree.

Claim 5

Apparatus as recited in claim 2 wherein the first and second charge transfer device storage cells comprise: a semiconductor substrate of a first conductivity type, a first and a second gate electrode disposed over a major surface of the substrate and insulated from the substrate, a first impurity zone of a second conductivity type formed in the substrate partially under the first gate electrode and partially under the second gate electrode, a second impurity zone of a second conductivity type formed in the substrate partially under the first gate electrode and having substantially more area under the first gate electrode than the first impurity region, and a third impurity zone of a second conductivity type formed in the substrate partially under the second gate electrode and having substantially more area under the second gate electrode than the first impurity region.

Claim 6

An apparatus as recited in claim 1 further comprising: charge transfer device output means and means for applying shift control to the charge transfer device output means included in the conversion means for taking the output data streams from the 2M shift register output nodes and successively combining alternate bits of data from two output data streams into one output data stream until there is an M-level logic tree formed with a single output data stream, the shift control having a different repetition rate at different levels of the output logic tree.

Claim 7

Apparatus as recited in claim 5 wherein the charge transfer device output means for combining a first output data stream flowing in a first output path and a second output data stream flowing in a second output path into a third output data stream flowing in a third output path comprises: a first charge transfer device storage cell having a shift terminal, an input node connected to the first output path, and an output node connected to the third output path, a second charge trAnsfer device storage cell having a shift terminal, an input node connected to the second output path and an output node connected to the third output path, and shift means connected to the shift terminals for producing a shift signal to repetitively make both charge transfer device storage cells alternately conducting and nonconducting.

Claim 8

Apparatus as recited in claim 6 wherein the shift means comprises means to double the repetition rate of the shift signal applied to charge transfer device storage cells at each successive level of the output logic tree.

Claim 9

Apparatus as recited in claim 6 wherein the first and second charge transfer device storage cells comprise: a semiconductor substrate of a first conductivity type, a first and a second gate electrode disposed over a major surface of the substrate and insulated from the substrate, a first impurity zone of a second conductivity type formed in the substrate partially under the first gate electrode, a second impurity zone of a second conductivity type formed in the substrate partially under the second gate electrode, and a third impurity zone of a second conductivity type formed in the substrate partially under the first gate electrode with substantially more area under the first electrode than the first impurity region and partially under the second gate electrode with substantially more area under the second gate electrode than the second impurity region.

Claim 10

A charge transfer device shift register comprising 2M (M is an integer greater than one) parallel intermediate shift registers each register having an input node to receive an input data stream and an output node to provide an output data stream, and conversion means for combining output data streams from the output nodes into a single output data stream, wherein the improvement comprises: charge transfer device output means and means for applying shift control to the charge transfer device output means included in the conversion means for taking the output data streams from the 2M shift register output nodes and successively combining alternate bits of data from two output data streams into one output data stream until there is an M-level logic tree formed with a single output data stream, the shift control having a different repetition rate at different levels of the output logic tree.

Claim 11

A charge transfer device shift register comprising 2M (M is an integer greater than one) parallel intermediate shift registers each register having an input node to receive an input data stream and an output node to provide an output data stream, and conversion means for combining output data streams from the output nodes into a single output data stream, wherein the improvement comprises: charge transfer device output means and means for applying shift control to the charge transfer device output means included in the conversion means for taking the output data streams from the 2M shift register output nodes and successively combining alternate bits of data from two output data streams into one output data stream until there is an M-level logic tree formed with a single output data stream, the shift control having a different repetition rate at different levels of the output logic tree.

Claim 12

Apparatus as recited in claim 9 wherein the charge transfer device output means for combining a first output data stream flowing in a first output path and a second output data stream flowing in a second output path into a third output data stream flowing in a third output path comprises: a first charge transfer device storage cell having a shift terminal, an input node connected to the first output path, and an output node connected to the third output path, a second charge transfer device storage cell having a shift terminal, an input node connected to the second output path and an output node connected to the third output path, and shift means connected to the shift terminals for producing a shift signal to repetitively make both charge transfer device storage cells alternately conducting and nonconducting.

Claim 13

Apparatus as recited in claim 10 wherein the shift means comprises means to double the repetition rate of the shift signal applied to charge transfer device storage cells at each successive level of the output logic tree.

Claim 14

Apparatus as recited in claim 10 wherein the first and second charge transfer device storage cells comprises: a semiconductor substrate of a first conductivity type, a first and a second gate electrode disposed over a major surface of the substrate and insulated from the substrate, a first impurity zone of a second conductivity type formed in the substrate partially under the first gate electrode, a second impurity zone of a second conductivity type formed in the substrate partially under the second gate electrode, and a third impurIty zone of a second conductivity type formed in the substrate partially under the first gate electrode with substantially more area under the first electrode than the first impurity region and partially under the second gate electrode with substantially more area under the second gate electrode than the second impurity region.

Claim 17

A method as recited in claim 13 wherein the division of alternate bits of data from one data stream between two data streams is provided by: applying the data of one data stream to the input nodes of a first and a second charge transfer device storage cell, and controlling a data stream at each of the outputs of the two charge transfer device storage cells by applying a shift signal to each of the charge transfer device storage cells to repetitively make the first charge transfer device storage cell conducting while the second charge transfer device storage cell is nonconducting, and to repetitively make the second charge transfer device storage cell conducting while the first charge transfer device storage cell is nonconducting.

Claim 18

A method as recited in claim 14 wherein the shift signal applied to the charge transfer device storage cells is provided by halving the repetition rate of the shift signal applied to charge transfer device storage cells at each successive division of the input data stream.

Claim 19

A method as recited in claim 14 wherein applying the data of one data stream to the input nodes of a first and a second charge transfer device storage cell is provided by: applying charge carriers representing data to an input impurity region of a first conductivity type in a substrate of a second conductivity type, the input impurity region forming the input of a first bucket brigade device storage cell and of a second bucket brigade device storage cell.

Claim 20

A method as recited in claim 14 wherein controlling a data stream at each of the outputs of the two charge transfer device storage cells is provided by: applying shift signals to the gate electrodes of a first and a second bucket brigade device storage cell thereby controlling the flow of charge carriers representing data between the input impurity region and the output impurity region of each bucket brigade device storage cell.

Claim 21

A method as recited in claim 13 further comprising: producing an output data stream at each of the output nodes of the 2M parallel, intermediate, charge transfer device shift registers, and combining successively M times using an output charge transfer device alternate bits of data from two output data streams into one output data stream until there is a single output data stream wherein said combining step includes the step of applying to the output charge transfer device shift control having a different repetition rate at different successive combinations.

Claim 22

A method as recited in claim 18 wherein the successive combination of bits of data from a first and a second output data stream into a third output data stream is provided by: applying the first output data stream to the input of a first charge transfer device storage cell, applying the second oUtput data stream to the input of a second charge transfer device storage cell having a common output with the first charge transfer device storage cell, and controlling the third output data stream at the common output of the two charge transfer device storage cells by applying a shift signal to each of the charge transfer device storage cells alternately making both charge transfer device cells conducting and nonconducting.

Claim 23

A method as recited in claim 19 wherein successive combination of bits of data from a first and a second output data stream into a third output data stream is provided by: applying charge carriers representing data of a first output stream to a first impurity region forming the input of a first bucket brigade device storage cell, applying charge carriers representing data of a second output stream to a second impurity region forming the input of a second bucket brigade device storage cell having a common output impurity region with the first bucket brigade device storage cell, and controlling the flow of charge carriers to the output impurity region by applying a shift signal to the gate electrodes of each of the bucket brigade device storage cells alternately making both bucket brigade device storage cells conducting and nonconducting.

Claim 24

A method as recited in claim 19 wherein the shift signal applied to the charge transfer device storage cells is provided by doubling the repetition rate of the shift signal applied to charge transfer device storage cells at each successive combination of output data streams.

Claim 27

A method as recited in claim 22 wherein the successive combination of bits of data from a first and a second output data stream into a third output data stream is provided by: applying the first output data stream to the input of a first charge transfer device storage cell, applying the second output data stream to the input of a second charge transfer device storage cell having a common output with the first charge transfer device storage cell, and controlling the third output data stream at the common output of the two charge transfer device storage cells by applying a shift signal to each of the charge transfer device storage cells alternately making both charge transfer device storage cells conducting and nonconducting.

Claim 28

A method as recited in claim 23 wherein a shift signal applied to the charge transfer device storage cells is provided by doubling the repetition rate of the shift signal applied to charge transfer device storage cells at each successive combination of output data streams.

Claim 29

A method as recited in claim 23 wherein successive combination of bits of data from a first and a second output data stream into a third output data stream is provided: applying charge carriers representing data of a first output stream to a first impurity region forming the input of a first bucket brigade device storage cell, applying charge carriers representing data of a second output stream to a second impurity region forming the input of a second bucket brigade device storage cell having a common output impurity region with the first bucket brigade device storage cell, and controlling the flow of charge carriers to the output impurity region by applying a shift signal to the gate electrode of each of the bucket brigade device storage cells alternately making both bucket brigade device storage cells conducting and nonconducting.