US3789240A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bucket brigade scanning of sensor array
Assignee: RCA Corp
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Filing: 1972-05-26
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Granted: 1974-01-29
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Expires: 1992-05-26
Abstract
Abstract A sensor array having photosensitive elements formed as an integral part of each stage of a shift register chain. Each stage has charge storage means. The photosensitive elements are coupled to the charge storage means for discharging them as a function of externally applied photo signals and, consequently, developing charge deficits in said charge storage means. The shift register, in response to a clocking signal, transfers the charge deficits from one stage to the next along the chain producing a serial output signal at an output terminal.
Inventors
- 👤 P Weimer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:40
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/891; H10D84/895; H04; H04N; H04N25/00; H04N25/70; H04N25/76; H04N25/767; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/15; H10F39/153
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
216 words
A scan generator comprising: N transistors each transistor having first and second electrodes defining the ends of a conduction path and a control electrode whose applied potential determines the conductivity of said path; a capacitor per transistor, coupled between the control electrode and the second electrode of the transistor; means connecting the conduction paths of said transistors in series between a signal input point and a terminating transistor, the first of said N transistors having its first electrode connected to said signal input point; one output point per transistor, except for the terminating transistor, connected to the second electrode of each transistor for producing thereat an output pulse; first and second terminals connected to receive complementary enabling signals for enabling every other transistor during a first time interval and enabling the remaining transistors during a succeeding time interval: means for coupling said first terminal to the control electrode of every other transistor; means for coupling said second terminal to the control electrode of the remaining transistors; means for: 1. applying a voltage level to said signal input point having a polarity to allow conduction between the first and second electrodes of said first and succeeding transistors, when said transistors are enabled, for generating an approximately constant voltage level at each one of said output points; and
Claim 2
Dependent Claim
216 words
A scan generator comprising: N transistors each transistor having first and second electrodes defining the ends of a conduction path and a control electrode whose applied potential determines the conductivity of said path; a capacitor per transistor, coupled between the control electrode and the second electrode of the transistor; means connecting the conduction paths of said transistors in series between a signal input point and a terminating transistor, the first of said N transistors having its first electrode connected to said signal input point; one output point per transistor, except for the terminating transistor, connected to the second electrode of each transistor for producing thereat an output pulse; first and second terminals connected to receive complementary enabling signals for enabling every other transistor during a first time interval and enabling the remaining transistors during a succeeding time interval: means for coupling said first terminal to the control electrode of every other transistor; means for coupling said second terminal to the control electrode of the remaining transistors; means for: 1. applying a voltage level to said signal input point having a polarity to allow conduction between the first and second electrodes of said first and succeeding transistors, when said transistors are enabled, for generating an approximately constant voltage level at each one of said output points; and
Claim 3
Dependent Claim
100 words
Selectively blocking conduction between the first and second electrodes of said first transistor, when the enabling signal applied to the control electrode of said first transistor is in a direction to turn it on, whereby said enabling signal is coupled through the capacitor connected between the control electrode and the second electrode of the first transistor for producing an output pulse at the output point of said first transistor and whereby output pulses of substantially equal amplitude and having the same polarity are then sequentially produced at each succeeding one of said output points in response to said enabling signals.
Claim 4
Dependent Claim
100 words
Selectively blocking conduction between the first and second electrodes of said first transistor, when the enabling signal applied to the control electrode of said first transistor is in a direction to turn it on, whereby said enabling signal is coupled through the capacitor connected between the control electrode and the second electrode of the first transistor for producing an output pulse at the output point of said first transistor and whereby output pulses of substantially equal amplitude and having the same polarity are then sequentially produced at each succeeding one of said output points in response to said enabling signals.
Claim 5
Dependent Claim
100 words
Selectively blocking conduction between the first and second electrodes of said first transistor, when the enabling signal applied to the control electrode of said first transistor is in a direction to turn it on, whereby said enabling signal is coupled through the capacitor connected between the control electrode and the second electrode of the first transistor for producing an output pulse at the output point of said first transistor and whereby output pulses of substantially equal amplitude and having the same polarity are then sequentially produced at each succeeding one of said output points in response to said enabling signals.
Claim 6
Dependent Claim
100 words
Selectively blocking conduction between the first and second electrodes of said first transistor, when the enabling signal applied to the control electrode of said first transistor is in a direction to turn it on, whereby said enabling signal is coupled through the capacitor connected between the control electrode and the second electrode of the first transistor for producing an output pulse at the output point of said first transistor and whereby output pulses of substantially equal amplitude and having the same polarity are then sequentially produced at each succeeding one of said output points in response to said enabling signals.
Claim 7
Dependent Claim
19 words
The combination as claimed in claim 1 wherein said transistors are insulated-gate field-effect transistors of the same conDuctivity type.
Claim 8
Dependent Claim
15 words
The combination as claimed in claim 2 wherein said transistors are on a common substrate.
Claim 9
Dependent Claim
58 words
The combination as claimed in claim 1 wherein the output pulses are non-overlapping, the rising edge of a given pulse being concurrent in time with the falling edge of the pulse preceeding said given pulse and the falling edge of said given pulse being concurrent in time with the rising edge of the pulse succeeding said given pulse.
Claim 10
Independent Claim
298 words
A method for producing sequentially spaced contiguous pulses utilizing a charge transfer register comprised of N transistors, each transistor having first and second electrodes defining the ends of a conduction path and a control electrode whose applied potential determines the conductivity of said path; a capacitor per transistor coupled between the control electrode and the second electrode of the transistor; means connecting the conduction paths of said transistors in series between a signal input point and a terminating transistor, the first of said N transistors having its first electrode connected to said signal input point; one output point per transistor, except for the terminating transistor, connected to the second electrode of each transistor for producing thereat output pulses; first and second terminals; means for coupling said first terminal to the control electrode of every other transistor; means for coupling said second terminal to the control electrode of the remaining transistors; said method comprising the steps of: 1) applying alternating enabling segnals to said first terminal and the complement of said alternating enabling signals to said second terminal for during a first time interval enabling every other transistor and during a succeeding time interval enabling the remaining transistors; 2) applying a first voltage level to said signal input point having a polarity and magnitude to render said first transistor as well as all succeeding transistors conducting, when enabled, for producing an approximately constant voltage level at each one of said output points, and 3) selectively applying a pulse to said signal input point having a polarity and magnitude to prevent conduction in said first transistor when said first transistor is enabled for producing an output pulse at the output of said first transistors which is then sequentially propagated along succeeding output points on each alternation of said enabling signals.
Claim 11
Independent Claim
298 words
A method for producing sequentially spaced contiguous pulses utilizing a charge transfer register comprised of N transistors, each transistor having first and second electrodes defining the ends of a conduction path and a control electrode whose applied potential determines the conductivity of said path; a capacitor per transistor coupled between the control electrode and the second electrode of the transistor; means connecting the conduction paths of said transistors in series between a signal input point and a terminating transistor, the first of said N transistors having its first electrode connected to said signal input point; one output point per transistor, except for the terminating transistor, connected to the second electrode of each transistor for producing thereat output pulses; first and second terminals; means for coupling said first terminal to the control electrode of every other transistor; means for coupling said second terminal to the control electrode of the remaining transistors; said method comprising the steps of: 1) applying alternating enabling segnals to said first terminal and the complement of said alternating enabling signals to said second terminal for during a first time interval enabling every other transistor and during a succeeding time interval enabling the remaining transistors; 2) applying a first voltage level to said signal input point having a polarity and magnitude to render said first transistor as well as all succeeding transistors conducting, when enabled, for producing an approximately constant voltage level at each one of said output points, and 3) selectively applying a pulse to said signal input point having a polarity and magnitude to prevent conduction in said first transistor when said first transistor is enabled for producing an output pulse at the output of said first transistors which is then sequentially propagated along succeeding output points on each alternation of said enabling signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-28 | 1977-07-30 | 1978-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-28 | 1981-07-30 | 1982-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-28 | 1985-07-30 | 1986-01-29 | $7700.00 | Window Closed / Lapsed |