US4798981A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input circuit
Assignee: Toshiba Corp
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Filing: 1987-03-20
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Granted: 1989-01-17
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Expires: 2007-03-20
Abstract
Abstract An input circuit is disclosed, which can be driven by a single power supply, and which can convert an ECL-level input signal falling to a negative voltage into a CMOS-level signal rising to a positive voltage, and can then supply this CMOS-level signal to an inner circuit. The input circuit comprises a transistor, a bias circuit, and a current-to-voltage converter. The emitter of the transistor is coupled to an input terminal for receiving a signal of a negative potential. The bias circuit applies a negative bias voltage to the base of the transistor. The current-to-voltage converter is connected to the collector of the transistor. The converter outputs a signal which first falls to a positive level and then rises to another positive level. That is, the input circuit can convert an input signal of a negative level to a signal of a positive level.
Inventors
- 👤 Kazunori Tsugaru
- 👤 Yasuhiro Sugimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:19
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/017509; H03K19/017518; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
193 words
An input circuit driven by a single power supply for providing an output signal at a non-negative CMOS potential level to an inner circuit, comprising: an input terminal for receiving an input signal at a negative ECL potential level; means for providing the output signal at a non-negative CMOS potential level to the inner circuit; a first transistor having an emitter, a collector, and a base, whose collector is coupled to the output signal providing means; bias means coupled to the single power supply for applying a fixed bias voltage at a negative potential level to the base of said first transistor; regulator means coupling the input terminal to the emitter of the first transistor, for regulating the amount of collector current of the first transistor; and current-to-voltage converting means, coupling the output signal providing means and the collector of the first transistor to the single power supply, for generating the output signal at a higher non-negative potential level when the first transistor is turned off by the input signal and for generating the output signal at a lower non-negative potential level when the first transistor is turned on by the input signal.
Claim 2
Dependent Claim
193 words
An input circuit driven by a single power supply for providing an output signal at a non-negative CMOS potential level to an inner circuit, comprising: an input terminal for receiving an input signal at a negative ECL potential level; means for providing the output signal at a non-negative CMOS potential level to the inner circuit; a first transistor having an emitter, a collector, and a base, whose collector is coupled to the output signal providing means; bias means coupled to the single power supply for applying a fixed bias voltage at a negative potential level to the base of said first transistor; regulator means coupling the input terminal to the emitter of the first transistor, for regulating the amount of collector current of the first transistor; and current-to-voltage converting means, coupling the output signal providing means and the collector of the first transistor to the single power supply, for generating the output signal at a higher non-negative potential level when the first transistor is turned off by the input signal and for generating the output signal at a lower non-negative potential level when the first transistor is turned on by the input signal.
Claim 3
Dependent Claim
39 words
An input circuit according to claim 1, further comprising clamping means coupled to the single power supply and to the collector of the first transistor, for preventing a collector potential of said first transistor from falling below ground potential.
Claim 4
Dependent Claim
51 words
An input circuit according to claim 1, wherein said bias means includes a second transistor whose base is biased by an output of said clamping means, and a resistor connecting the emitter of said first transistor to the base of said first transistor and to an emitter of said second transistor.
Claim 5
Dependent Claim
38 words
An input circuit according to claim 2, wherein said clamping means includes a third transistor supplied with power from said single power supply, an emitter of said third transistor being coupled to the collector of said first transistor.
Claim 6
Dependent Claim
58 words
An input circuit according to claim 1, wherein said current-to-voltage converting means includes a P-channel MOS transistor supplied with power from said single power supply, a drain of said P-channel MOS transistor being coupled to the collector of said first transistor, and a gate and the drain of said P-channel MOS transistor being directly coupled to each other.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-17 | 1992-07-18 | 1993-01-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-17 | 1996-07-18 | 1997-01-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-17 | 2000-07-18 | 2001-01-17 | $7700.00 | Window Closed / Lapsed |