US4713600A
Expired / Lapsed
US
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Level conversion circuit
Assignee: Toshiba Corp
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Filing: 1986-09-19
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Granted: 1987-12-15
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Expires: 2006-09-19
Abstract
Abstract This invention provides a level conversion circuit comprising: an input terminal means for applying a voltage signal of predetermined amplitude level; an inverter circuit means applied by a first power supply and a second power supply and connected to the input terminal; a first MOS transistor of a first channel type, the source of which is connected to the second power supply, and the gate of which is connected to the output of the inverter circuit means; a current-voltage conversion means for converting from a source-drain current change of the first MOS transistor to voltage change, a first terminal of which is connected to the drain of the first MOS transistor, and a second terminal of which is connected to a third power supply; a second MOS transistor of the second channel type, the source of which is connected to the third power supply, and the gate of which is connected to the first terminal of the current-voltage conversion means; a third MOS transistor of the first channel type, the gate of which is connected to the input terminal, and source of which is connected to the second power supply, and drain of which is connected to the drain of the second MOS transistor; and an output terminal means for supplying a signal, the amplitude level of which is different from that of the voltage level corresponding to the signal applied to the input terminal, which is connected to the drain of the third MOS transistor.
Inventors
- 👤 Kazunori Tsugaru
- 👤 Yasuhiro Sugimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:31
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K5/00; H03K5/01; H03K5/02; H03K5/023
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
291 words
A level conversion circuit comprising: an input terminal means for applying a voltage signal of predetermined amplitude level; an inverter circuit means applied by a first power supply and a second power supply and connected to said input terminal; a first MOS transistor of a first channel type, the source of which is connected to said second power supply, and the gate of which is connected to the output of said inverter circuit means; a current-voltage conversion means for converting from a source-drain current change of said first MOS transistor to voltage change, a first terminal of which is connected to the drain of said first MOS transistor, and a second terminal of which is connected to a third power supply; a second MOS transistor of a second channel type, the source of which is connected to said third power supply, and the gate of which is connected to the first terminal of said current-voltage conversion means; a third MOS transistor of the first channel type, the gate of which is connected to said input terminal, and source of which is connected to said second power supply, and drain of which is connected to the drain of said second MOS transistor; and an output terminal means for supplying a signal, the amplitude level of which is different from that of the voltage level corresponding to the signal applied to said input terminal, which is connected to the drain of said third MOS transistor; wherein said current-voltage conversion means is a fourth MOS transistor of the second channel type, the source of which is connected to a third power supply, and the drain and gate of which are shorted to form a common connection to the drain of said first MOS transistor.
Claim 2
Dependent Claim
291 words
A level conversion circuit comprising: an input terminal means for applying a voltage signal of predetermined amplitude level; an inverter circuit means applied by a first power supply and a second power supply and connected to said input terminal; a first MOS transistor of a first channel type, the source of which is connected to said second power supply, and the gate of which is connected to the output of said inverter circuit means; a current-voltage conversion means for converting from a source-drain current change of said first MOS transistor to voltage change, a first terminal of which is connected to the drain of said first MOS transistor, and a second terminal of which is connected to a third power supply; a second MOS transistor of a second channel type, the source of which is connected to said third power supply, and the gate of which is connected to the first terminal of said current-voltage conversion means; a third MOS transistor of the first channel type, the gate of which is connected to said input terminal, and source of which is connected to said second power supply, and drain of which is connected to the drain of said second MOS transistor; and an output terminal means for supplying a signal, the amplitude level of which is different from that of the voltage level corresponding to the signal applied to said input terminal, which is connected to the drain of said third MOS transistor; wherein said current-voltage conversion means is a fourth MOS transistor of the second channel type, the source of which is connected to a third power supply, and the drain and gate of which are shorted to form a common connection to the drain of said first MOS transistor.
Claim 3
Dependent Claim
16 words
A level conversion circuit according to claim 1 wherein said inverter circuit is a CMOS inverter.
Claim 4
Dependent Claim
278 words
A level conversion circuit comprising: an input terminal means for applying a voltage signal of predetermined amplitude level; an inverter circuit means applied by a first power supply and a second power supply and connected to said input terminal; a first MOS transistor of a first channel type, the source of which is connected to said second power supply, and the gate of which is connected to the output of said inverter circuit means; a current-voltage conversion means for converting from a source-drain current change of said first MOS transistor to voltage change, a first terminal of which is connected to the drain of said first MOS transistor, and a second terminal of which is connected to a third power supply; a second MOS transistor of a second channel type, the source of which is connected to said third power supply, and the gate of which is connected to the first terminal of said current-voltage conversion means; a third MOS transistor of the first channel type, the gate of which is connected to said input terminal, and source of which is connected to said second power supply, and drain of which is connected to the drain of said second MOS transistor; and an output terminal means for suppling a signal, the amplitude level of which is different from that of the voltage level corresponding to the signal applied to said input terminal, which is connected to the drain of said third MOS transistor; wherein said current-voltage conversion means includes a resistance, a first terminal of which is connected the drain of said first MOS transistor, and a second terminal of which is connected to said third power supply.
Claim 5
Dependent Claim
278 words
A level conversion circuit comprising: an input terminal means for applying a voltage signal of predetermined amplitude level; an inverter circuit means applied by a first power supply and a second power supply and connected to said input terminal; a first MOS transistor of a first channel type, the source of which is connected to said second power supply, and the gate of which is connected to the output of said inverter circuit means; a current-voltage conversion means for converting from a source-drain current change of said first MOS transistor to voltage change, a first terminal of which is connected to the drain of said first MOS transistor, and a second terminal of which is connected to a third power supply; a second MOS transistor of a second channel type, the source of which is connected to said third power supply, and the gate of which is connected to the first terminal of said current-voltage conversion means; a third MOS transistor of the first channel type, the gate of which is connected to said input terminal, and source of which is connected to said second power supply, and drain of which is connected to the drain of said second MOS transistor; and an output terminal means for suppling a signal, the amplitude level of which is different from that of the voltage level corresponding to the signal applied to said input terminal, which is connected to the drain of said third MOS transistor; wherein said current-voltage conversion means includes a resistance, a first terminal of which is connected the drain of said first MOS transistor, and a second terminal of which is connected to said third power supply.
Claim 6
Dependent Claim
16 words
A level conversion circuit according to claim 3, wherein said inverter circuit is a CMOS inverter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-12-14 | 1991-06-15 | 1991-12-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-12-14 | 1995-06-15 | 1995-12-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-12-14 | 1999-06-15 | 1999-12-15 | $7700.00 | Window Closed / Lapsed |