Synchronizing circuit

Claim 1

A synchronizing circuit comprising: input pulse detecting means for detecting the arrival of an externally applied input pulse signal and generating a pulse signal of a predetermined width; a first bistable circuit; first latch means for latching the output signal from said first bistable circuit, in synchronism with a first internal clock signal; second latch means for latching the output signal of said first bistable circuit, in synchronism with a second internal clock signal, which is different in phase from said first internal clock signal; reset signal generating means which responds to the output signal from one of said first and second latch means which executed the latching operation, and supplies a reset signal to said first bistable circuit during a period of generation of the clock signal corresponding to the latch means which did not execute the latching operation; output means for outputting the output signal from said reset signal generating means, in synchronism with one of said first and second clock signals; and pulse signal transfer control means, which receives the pulse signal output from said detecting means, prohibits said pulse signal from being transferred to said first bistable circuit during a period in which said first bistable circuit is set, a period of generation of said first clock signal, and a period of generation of said second clock signal, and allows the pulse signal to be transferred to said first bistable circuit during a period in which said first and second clock signals are not generated and said period in which said first bistable circuit is reset.