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US4797001A Expired / Lapsed US ⏱️ 0.0 years remaining

Substrate bias generator for use in dynamic random access memory

Assignee: Mitsubishi Electric Corp
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Filing: 1987-07-29
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Granted: 1989-01-10
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Expires: 2007-07-29
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Abstract

Abstract The invention relates to a substrate bias generator for use in dynamic random access memory, and in which either a plurality of transistors for rectification are disposed between a coupling capacitor and a substrate potential electrode or a threshold voltage of a transistor for rectification between the coupling capacitor and the substrate potential electrode is different from a threshold voltage of the other transistor making the absolute value of substrate potential smaller thereby, so that a depletion-layer distance formed between a P-type substrate and N + -type substrate is shortened and that effect due to incidence of α-particle is reduced resulting in reducing soft error rate.

Inventors

  • 👤 Noriaki Matsumoto
  • 👤 Koichiro Mashiko
  • 👤 Kazutami Arimoto
  • 👤 Kiyohiro Furutani
  • 👤 Yoshio Matsuda

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 17:48
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 134 words
A substrate bias generator for setting a potential of a semiconductor substrate in a dynamic random access memory and reducing soft errors such as errors caused by alpha ray irradiation, in an IC having insulated gate type field effect transistors (IGFET) as the fundamental elements, said substrate bias generator comprising: substrate potential generating means provided for generating a substrate potential, a coupling capacitor connected to an output of said substrate potential generating means, an IGFET transistor for rectification provided between said coupling capacitor and a ground potential, substrate potential control means provided between said coupling capacitor and a substrate potential electrode for controlling the substrate potential to maintain a required level, said substrate potential control means comprising a plurality of IGFET transistors connected in series between said coupling capacitor and said substrate potential electrode.
Claim 2
Dependent Claim 134 words
A substrate bias generator for setting a potential of a semiconductor substrate in a dynamic random access memory and reducing soft errors such as errors caused by alpha ray irradiation, in an IC having insulated gate type field effect transistors (IGFET) as the fundamental elements, said substrate bias generator comprising: substrate potential generating means provided for generating a substrate potential, a coupling capacitor connected to an output of said substrate potential generating means, an IGFET transistor for rectification provided between said coupling capacitor and a ground potential, substrate potential control means provided between said coupling capacitor and a substrate potential electrode for controlling the substrate potential to maintain a required level, said substrate potential control means comprising a plurality of IGFET transistors connected in series between said coupling capacitor and said substrate potential electrode.
Claim 3
Dependent Claim 153 words
A substrate bias generator for setting a potential of a semiconductor substrate in a dynamic random access memory and reducing soft errors such as errors caused by alpha ray irradiation, in an IC having insulated gate type field effect transistors (IGFET) as the fundamental elements, said substrate bias generator comprising: substrate potential generating means provided for generating a substrate potential, a coupling capacitor connected to an output of said substrate potential generating means, a first IGFET transistor for rectification provided between said coupling capacitor and a ground potential, substrate potential control means provided between said coupling capacitor and a substrate potential electrode for controlling the substrate potential to maintain a required level, said substrate potential control means comprising a second IGFET transistor for rectification connected between said coupling capacitor and said substrate potential electrode said second transistor having a threshold voltage thereof different from a threshold voltage of said first transistor for rectification.
Claim 4
Dependent Claim 153 words
A substrate bias generator for setting a potential of a semiconductor substrate in a dynamic random access memory and reducing soft errors such as errors caused by alpha ray irradiation, in an IC having insulated gate type field effect transistors (IGFET) as the fundamental elements, said substrate bias generator comprising: substrate potential generating means provided for generating a substrate potential, a coupling capacitor connected to an output of said substrate potential generating means, a first IGFET transistor for rectification provided between said coupling capacitor and a ground potential, substrate potential control means provided between said coupling capacitor and a substrate potential electrode for controlling the substrate potential to maintain a required level, said substrate potential control means comprising a second IGFET transistor for rectification connected between said coupling capacitor and said substrate potential electrode said second transistor having a threshold voltage thereof different from a threshold voltage of said first transistor for rectification.

References Cited (Backward Citations)

US4233672A Cited
US4559694A Cited
US4455628A Cited
JPS5914665A Cited
JPS6038028A Cited
US4691304A Cited
US4695746A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-01-10 1992-07-11 1993-01-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-01-10 1996-07-11 1997-01-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-01-10 2000-07-11 2001-01-10 $7700.00 Window Closed / Lapsed

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