Dynamic read-write random access memory

Claim 2

A dynamic read-write random access memory, comprising; a memory cell including, a supply voltage terminal, a capacitive means having a first charge terminal connected to said supply voltage terminal and a second charge terminal, and switching means, having a first conduction terminal connected to said second charge terminal and a second conduction terminal, for forming a conduction path between said first and second conduction terminals, said switching means having a control terminal for controlling the impedance of said conduction path; a word line connected to said control terminal, said word line having a first voltage level when said memory cell is selected and second voltage level when said memory cell is not selected; a bit line connected to said second conduction terminal; and, voltage applying means for applying to said bit line a voltage level comprising, a MOS transistor having source, drain and gate terminals; and a first diode connected in series with said source and drain terminals between a pair of voltage sources, said gate terminal connected to that voltage source connected to said diode, wherein the voltage level applied by said voltage level applying means is derived from a junction between the source-drain path of said transistor and said diode, between said second voltage level of said word line and a voltage level of said first conduction terminal when said memory cell is not selected, thereby preventing leakage current from flowing through said conduction path when said memory cell is not selected.

Claim 3

A dymanic read-write random access memory according to claim 1, further comprising: means for detecting a change of voltage level of said bit line when said memory cell is selected.

Claim 4

A dynamic read-write random access memory according to claim 2, wherein said switching means comprises: a transistor.

Claim 5

A dynamic read-write random access memory according to claim 3, wherein said transistor comprises: a MOS transistor.

Claim 6

A dynamic read-write random access memory according to claim 2, wherein said detecting means comprises: a differential amplifier having a first input terminal connected to said bit line and a second input terminal connected to a reference voltage.

Claim 7

A dynamic read-write random access memory according to claim 5, wherein said differential amplifier comprises: a pair of cross-coupled MOS transistors having a common source connection and having the gate of each MOS transistor connector to the drain of the other MOS transistor.

Claim 8

A dynamic read-write random access memory according to claim 6, further comprising: a switching transistor having a first conduction terminal connected to said common source connection and a second conduction terminal connected to an output terminal of said voltage applying means, said switching transistor rendered conductive when said memory cell is selected.

Claim 9

A dynamic read-write random access memory according to claim 5, wherein said second input terminal of said differential amplifier is supplied with a reference power source having a predetermined reference voltage level.

Claim 10

A dynamic read-write random access memory according to claim 5, further comprising: a dummy cell connected to said second input terminal of said differential amplifier.

Claim 11

A dynamic read-write random access memory according to claim 2, further comprising: precharge means for precharging said bit line.

Claim 12

A dynamic read-write random access memory according to claim 1, wherein said voltage level applying means comprises: a second diode connected in series with said first diode.

Claim 13

A dynamic read-write random access memory according to claim 1, wherein said voltage applying means comprises: first and second MOS transistors having source drain paths connected in series between first and second voltage sources; a first inverter having an input connected to a junction between the source-drain paths of said first and second MOS transistors, and an output; a second inverter circuit having an input connected to the output of said first inverter circuit and an output connected to the gate of said second MOS transistor, wherein the gate of said first MOS transistor is connected to a selected of said first and second voltage sources and said voltage level applied by said voltage level applying means is derived from said function.

Claim 14

A dynamic read-write random access memory, comprising: a first memory cell including, a supply voltage terminal, a first capacitive means having a first charge terminal connected to said supply voltage terminal and a second charge terminal, and a first switching means, having a first conduction terminal connected to said second charge terminal of said first capacitive means and a second conduction terminal, for forming a conduction path between said first and second conduction terminals, said first switching means having a control terminal for controlling the impedance of said conduction path; a first word line connected to said control terminal of said first switching means, said first word line having a first voltage level when said first memory cell is selected and a second voltage level when said first memory cell is not selected; a first bit line connected to said second conduction terminal of said first switching means; a second memory cell including, a supply voltage terminal, a second capacitive means having a first charge terminal connected to said second charge terminal of said second capacitance means and a second conduction terminal, for forming a conduction path between said first and second terminals of said second switching means, said second switching means having a control terminal for controlling the impedance of the conduction path thereof; a second word line connected to said control terminal of said second switching means, said second word line having a first voltage level when said second memory cell is selected and a second voltage level when said second memory cell is not selected; a second bit line connected to said second conduction terminal of said second memory cell; a differential amplifier including a pair of cross-coupled MOS transistors having drains respectively connected to said first bit line and said second bit line, a common source connection, and respective gates connected to the drain of the other MOS transistor of said pair; and voltage level applying means for applying to said first bit line a voltage level between the voltage level of said word line and the voltage level of said first conduction terminal of said first memory cell when said first memory cell is not selected, thereby preventing a leakage current from flowing through said conduction path of said first memory cell when said first memory cell is not selected.

Claim 15

A dynamic read-write random access memory, comprising: a first memory cell including, a supply voltage terminal, a first capacitive means having a first charge terminal connected to said supply voltage terminal and a second charge terminal, and a first switching means, having a first conduction terminal connected to said second charge terminal of said first capacitive means and a second conduction terminal, for forming a conduction path between said first and second conduction terminals, said first switching means having a control terminal for controlling the impedance of said conduction path; a first word line connected to said control terminal of said first switching means, said first word line having a first voltage level when said first memory cell is selected and a second voltage level when said first memory cell is not selected; a first bit line connected to said second conduction terminal of said first switching means; a second memory cell including, a supply voltage terminal, a second capacitive means having a first charge terminal connected to said second charge terminal of said second capacitance means and a second conduction terminal, for forming a conduction path between said first and second terminals of said second switching means, said second switching means having a control terminal for controlling the impedance of the conduction path thereof; a second word line connected to said control terminal of said second switching means, said second word line having a first voltage level when said second memory cell is selected and a second voltage level when said second memory cell is not selected; a second bit line connected to said second conduction terminal of said second memory cell; a differential amplifier including a pair of cross-coupled MOS transistors having drains respectively connected to said first bit line and said second bit line, a common source connection, and respective gates connected to the drain of the other MOS transistor of said pair; and voltage level applying means for applying to said first bit line a voltage level between the voltage level of said word line and the voltage level of said first conduction terminal of said first memory cell when said first memory cell is not selected, thereby preventing a leakage current from flowing through said conduction path of said first memory cell when said first memory cell is not selected.

Claim 16

A dynamic read-write random access memory according to claim 13, further comprising: a switching transistor having a first conduction terminal connected to said common source connection and a second conduction terminal connected to an output terminal of said voltage level applying means, said switching transistor rendered conductive when said first memory cell is selected; a first dummy cell connected to said first bit line; a second dummy cell connected to said second bit line; and precharge means for precharging said first and second bit lines.

Claim 17

A dynamic read-write random access memory according to claim 13, wherein said voltage level applying means comprises: a MOS transistor having source, drain and gate terminals; and a first diode connected in series with said source and drain terminals between a pair of voltage sources, said gate terminal connected to that voltage source connected to said diode, wherein the voltage level applied by said voltage level applying means is derived from a junction between the source-drain path of said transistor and said diode.

Claim 18

A dynamic read-write random access memory according to claim 15, wherein said voltage level applying means comprises: a second diode connected in series with said first diode.

Claim 19

A dynamic read-write random access memory according to claim 13, wherein said voltage level applying means comprises: first and second MOS transistors having source-drain paths connected in series between first and second voltage sources; a first inverter having an input connected to a junction between the source-drain paths of said first and second MOS transistors, and an output; a second inverter circuit having an input connected to the output of said first inverter circuit and an output connected to the gate of said second MOS transistor, wherein the gate of said first MOS transistor is connected to a selected one of said first and second voltage sources and said voltage level applied by said voltage level applying means is derived from said junction.

Claim 20

A dynamic read-write random access memory according to claim 13, further comprising: a switching transistor having a first conduction terminal connected to said common source connection and a second conduction terminal connected to an output terminal of said voltage level applying means, said switching transistor rendered conductive when said first memory cell is selected.

Claim 21

A dynamic read-write random access memory, comprising: a memory cell including, a supply voltage terminal, capacitive means having a first charge terminal connected to said supply voltage terminal and a second charge terminal, and switching means, having a first conduction terminal connected to said second charge terminal and a second conduction terminal, for forming a conduction path between said first and second conduction terminals, said switching means having a control terminal for controlling the impedance of said conduction path; a word line connected to said control terminal, said word line having a first voltage level when said memory cell is selected and a second voltage level when said memory cell is not selected; a bit line connected to said second conduction terminal; and means for bringing a voltage between said second voltage level of said word line and a voltage level of said bit line when said memory cell is not selected, thereby preventing leakage current from flowing through said conduction path when said memory cell is not selected.

Claim 22

A dynamic read-write random access memory, comprising: a memory cell including, a supply voltage terminal, capacitive means having a first charge terminal connected to said supply voltage terminal and a second charge terminal, and switching means, having a first conduction terminal connected to said second charge terminal and a second conduction terminal, for forming a conduction path between said first and second conduction terminals, said switching means having a control terminal for controlling the impedance of said conduction path; a word line connected to said control terminal, said word line having a first voltage level when said memory cell is selected and a second voltage level when said memory cell is not selected; a bit line connected to said second conduction terminal; and means for bringing a voltage between said second voltage level of said word line and a voltage level of said bit line when said memory cell is not selected, thereby preventing leakage current from flowing through said conduction path when said memory cell is not selected.