US4791471A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit device
Assignee: Fujitsu Ltd
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Filing: 1988-02-16
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Granted: 1988-12-13
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Expires: 2008-02-16
Abstract
Abstract In a semiconductor integrated circuit device, a plurality of a field effect transistors are formed on a (110) crystal surface of a group III-V compound semiconductor substrate having a zinc blend type crystal structure.
Inventors
- 👤 Tsukasa Onodera
- 👤 Haruo Kawata
- 👤 Toshiro Futatsugi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 02:40
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/87; H10D62/00; H10D62/40; H10D62/405; H10D62/80; H10D62/85; H10D84/00; H10D84/01; H10D84/02; H10D84/05
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
166 words
A semiconductor integrated circuit device, comprising: a compound semiconductor substrate formed of a group III-V compound semiconductor having a zinc blend type crystal structure, the surface of said compound semiconductor substrate being a (110) crystal surface; a plurality of field effect transistors, each including: source and drain regions formed at the surface of said compound semiconductor substrate and positioned such that the direction of a drain current is [001] with respect to said compound semiconductor substrate; and a gate electrode formed directly on the surface of said compound semiconductor substrate and between said source and drain regions, said gate electrode forming a Schottky contact with said compound semiconductor substrate; and an insulating layer formed on said gate electrode and directly on the surface of said compound semiconductor substrate adjacent to said gate electrode, said insulating layer exerting a tensile stress on said compound semiconductor substrate, the stress being applied to said compound semiconductor substrate at a boundary portion between said gate electrode and said insulating layer.
Claim 2
Dependent Claim
166 words
A semiconductor integrated circuit device, comprising: a compound semiconductor substrate formed of a group III-V compound semiconductor having a zinc blend type crystal structure, the surface of said compound semiconductor substrate being a (110) crystal surface; a plurality of field effect transistors, each including: source and drain regions formed at the surface of said compound semiconductor substrate and positioned such that the direction of a drain current is [001] with respect to said compound semiconductor substrate; and a gate electrode formed directly on the surface of said compound semiconductor substrate and between said source and drain regions, said gate electrode forming a Schottky contact with said compound semiconductor substrate; and an insulating layer formed on said gate electrode and directly on the surface of said compound semiconductor substrate adjacent to said gate electrode, said insulating layer exerting a tensile stress on said compound semiconductor substrate, the stress being applied to said compound semiconductor substrate at a boundary portion between said gate electrode and said insulating layer.
Claim 3
Dependent Claim
168 words
A semiconductor integrated circuit device comprising: a compound semiconductor substrate formed of a group III-V compound semiconductor having a zinc blend type crystal structure, a surface of said compound semiconductor substrate being a (110) crystal surface; a plurality of field effect transistors, each of said transistors including: source and drain regions formed at the surface of said compound semiconductor substrate and positioned such that the direction of a drain current is [001] with respect to said compound semiconductor substrate; and a gate electrode formed directly on the surface of said compound semiconductor substrate between said source and drain regions, said gate electrode forming a Schottky contact with said compound semiconductor substrate; and an insulating layer formed on said gate electrode and directly on the surface of said compound semiconductor substrate adjacent to said gate electrode, said insulating layer exerting a compression stress on said compound semiconductor substrate, a stress being applied to said compound semiconductor substrate at a boundary portion between said gate electrode and said insulating layer.
Claim 4
Dependent Claim
168 words
A semiconductor integrated circuit device comprising: a compound semiconductor substrate formed of a group III-V compound semiconductor having a zinc blend type crystal structure, a surface of said compound semiconductor substrate being a (110) crystal surface; a plurality of field effect transistors, each of said transistors including: source and drain regions formed at the surface of said compound semiconductor substrate and positioned such that the direction of a drain current is [001] with respect to said compound semiconductor substrate; and a gate electrode formed directly on the surface of said compound semiconductor substrate between said source and drain regions, said gate electrode forming a Schottky contact with said compound semiconductor substrate; and an insulating layer formed on said gate electrode and directly on the surface of said compound semiconductor substrate adjacent to said gate electrode, said insulating layer exerting a compression stress on said compound semiconductor substrate, a stress being applied to said compound semiconductor substrate at a boundary portion between said gate electrode and said insulating layer.
Claim 5
Dependent Claim
175 words
A semiconductor integrated circuit device comprising: a compound semiconductor substrate formed of a group III-V compound semiconductor having a zinc blend type crystal structure, the surface of said compound semiconductor substrate being a (110) crystal surface; a plurality of field effect transistors, each of said field effect transistors including: source and drain regions formed at the surface of said compound semiconductor substrate positioned in a direction such that a drain current flows in one of a [110] and [110] direction with respect to said compound semiconductor substrate; and a gate electrode formed directly on the surface of said compound semiconductor substrate between said source and drain regions, said gate electrode forming a Schottky contact with said compound semiconductor substrate; and an insulating layer formed on said gate electrode and directly on the surface of said compound semiconductor substrate adjacent to said gate electrode, said insulating layer exerting a stress on said compound semiconductor substrate, a stress being applied to said compound semiconductor substrate at a boundary portion between said gate electrode and said insulating layer.
Claim 6
Dependent Claim
175 words
A semiconductor integrated circuit device comprising: a compound semiconductor substrate formed of a group III-V compound semiconductor having a zinc blend type crystal structure, the surface of said compound semiconductor substrate being a (110) crystal surface; a plurality of field effect transistors, each of said field effect transistors including: source and drain regions formed at the surface of said compound semiconductor substrate positioned in a direction such that a drain current flows in one of a [110] and [110] direction with respect to said compound semiconductor substrate; and a gate electrode formed directly on the surface of said compound semiconductor substrate between said source and drain regions, said gate electrode forming a Schottky contact with said compound semiconductor substrate; and an insulating layer formed on said gate electrode and directly on the surface of said compound semiconductor substrate adjacent to said gate electrode, said insulating layer exerting a stress on said compound semiconductor substrate, a stress being applied to said compound semiconductor substrate at a boundary portion between said gate electrode and said insulating layer.
Claim 7
Dependent Claim
36 words
A semiconductor integrated circuit device including gate electrodes and scribe lines according to claim 1, wherein a chip layout is carried out so that the direction of the drain current is parallel to said scribe lines.
Claim 8
Dependent Claim
42 words
A semiconductor integrated circuit device including gate electrodes and scribe lines according to claim 1, wherein a chip layout is carried out so that the direction in which at least one of said gate electrodes extends is perpendicular to said scribe lines.
Claim 9
Dependent Claim
19 words
A semiconductor integrated circuit device according to claim 1, wherein said insulating layer is formed of SiO 2 .
Claim 10
Dependent Claim
21 words
A semiconductor integrated circuit device according to claim 2, wherein said insulating layer is formed of Si 3 N 4 .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1991-12-13 | 1992-06-13 | 1992-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-12-13 | 1996-06-13 | 1996-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-12-13 | 2000-06-13 | 2000-12-13 | $7700.00 | Window Closed / Lapsed |