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US4790920A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for depositing an al2 O3 cap layer on an integrated circuit substrate

Assignee: Intel Corp
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Filing: 1987-01-08
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Granted: 1988-12-13
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Expires: 2007-01-08
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Abstract

Abstract A process for depositing a layer of reactively sputtered aluminum oxide on a wafer is disclosed, having particular application in semiconductor fabrication. A wafer is provided with a layer of aluminum (or aluminum with 1% silicon) having a thickness of generally one micron, using common semiconductor fabrication techniques. The wafer with its aluminum layer is disposed within a vacuum chamber which has been evacuated. An argon sputtering gas is introduced into the chamber along with oxygen, such that aluminum oxide is formed in the plasma region and deposited on the aluminum layer. Using this technique, a 300 angstroms aluminum oxide layer is deposited over the existing aluminum layer on the wafer, thereby forming an aluminum oxide cap layer. The presence of the aluminum oxide cap layer has been found to significantly reduce the formation of mouse bites and notches, as well as initial film stress during fabrication.

Inventors

  • 👤 Brian M. Krzanich

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 02:41
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/6928; H10P14/6929; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6314; H10P14/6319; H10W; H10W74/00; H10W74/40; H10W74/43; H10P14/6938; H10P14/6939; H10P14/69391; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/952

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 209 words
A method for fabricating an integrated circuit wafer, comprising the steps of: (a) positioning a thermally oxidized silicon wafer on a substrate holding fixture in a vacuum chamber; (b) evacuating said vacuum chamber; (c) introducing argon gas into said vacuum chamber until a first sputtering pressure of about 6×10 -3 TORR. is attained; (d) depositing an aluminum layer on said silicon wafer by sputtering an aluminum target at said first sputtering pressure until said aluminum layer reaches a thickness of about 1 micron; (e) evacuating said vacuum chamber to a pressure in the mid 10 -7 TORR. range; (f) introducing a gas mixture of argon and oxygen into said vacuum chamber until a second sputtering pressure of about 1×10 -2 TORR. is reached; (g) depositing an aluminum oxide layer on said aluminum layer by sputtering said aluminum target at said second sputtering pressure until said aluminum oxide layer attains a thickness of about 300 Angstroms; (h) providing a desired resist pattern on said aluminum oxide layer; (i) etching said aluminum and aluminum oxide layers whereby said aluminum oxide layer prevents etching acids from forming mouse bites or notches in said aluminum layer; and (j) annealing said semi-conductor chip whereby said aluminum oxide layer manifests reduced film stress after heating.
Claim 2
Independent Claim 209 words
A method for fabricating an integrated circuit wafer, comprising the steps of: (a) positioning a thermally oxidized silicon wafer on a substrate holding fixture in a vacuum chamber; (b) evacuating said vacuum chamber; (c) introducing argon gas into said vacuum chamber until a first sputtering pressure of about 6×10 -3 TORR. is attained; (d) depositing an aluminum layer on said silicon wafer by sputtering an aluminum target at said first sputtering pressure until said aluminum layer reaches a thickness of about 1 micron; (e) evacuating said vacuum chamber to a pressure in the mid 10 -7 TORR. range; (f) introducing a gas mixture of argon and oxygen into said vacuum chamber until a second sputtering pressure of about 1×10 -2 TORR. is reached; (g) depositing an aluminum oxide layer on said aluminum layer by sputtering said aluminum target at said second sputtering pressure until said aluminum oxide layer attains a thickness of about 300 Angstroms; (h) providing a desired resist pattern on said aluminum oxide layer; (i) etching said aluminum and aluminum oxide layers whereby said aluminum oxide layer prevents etching acids from forming mouse bites or notches in said aluminum layer; and (j) annealing said semi-conductor chip whereby said aluminum oxide layer manifests reduced film stress after heating.
Claim 3
Dependent Claim 16 words
The method of claim 1, wherein said annealing temperature is between 460° C. and 520° C.
Claim 4
Dependent Claim 13 words
The method of claim 1, whereby initial film stress is reduced by 20%.
Claim 5
Dependent Claim 16 words
The method of claim 1, wherein said resist is photolithographically patterned on said aluminum oxide layer.
Claim 6
Dependent Claim 19 words
The method of claim 4, wherein said aluminum oxide layer provides increased absorption of light during said photolithographic patterning.
Claim 7
Dependent Claim 25 words
The method of claim 1, wherein deposition of said aluminum layer occurs at a rate of 1400 Å/min. using a power setting of 8.5 Kw.
Claim 8
Dependent Claim 26 words
The method of claim 1, wherein deposition of said aluminim oxide layer occurs at a rate of 115 Å/min. using a power setting of 2.5 Kw.
Claim 9
Dependent Claim 23 words
The method of claim 1, wherein said aluminum oxide layer is formed in the presence of 94% argon gas and 6% oxygen gas.
Claim 10
Independent Claim 195 words
A method for fabricating an integrated circuit wafer in order to reduce film stress, the formation of mouse bites and notches during an etching step and to increase light absorption during a patterning step, said method comprising the steps of: positioning a thermally oxidized silicon wafer on a substrate holding fixture in a vacuum chamber; introducing argon gas into said vacuum chamber until a first sputtering pressure of about 6×10 -3 TORR. is attained; depositing a layer of aluminum on said substrate by sputering with argon gas at said first sputtering pressure until said aluminum layer reaches a thickness of about 1 micron; depositing a layer of aluminum oxide on said aluminum layer by sputtering with an argon-oxygen gas mixture at a second pressure of about 1×10 -2 TORR. until said aluminum oxide layer attains a thickness of about 300 Angstroms; photolithographically patterning a resist such that said aluminum oxide layer provides increased absorption of light during photolithography; etching said aluminum and aluminum oxide layers, whereby said aluminum oxide layer reduces formation of mouse bites and notches on said aluminum layer; and annealing said semi-conductor chip whereby said aluminum oxide layer manifests reduced film stress.
Claim 11
Independent Claim 195 words
A method for fabricating an integrated circuit wafer in order to reduce film stress, the formation of mouse bites and notches during an etching step and to increase light absorption during a patterning step, said method comprising the steps of: positioning a thermally oxidized silicon wafer on a substrate holding fixture in a vacuum chamber; introducing argon gas into said vacuum chamber until a first sputtering pressure of about 6×10 -3 TORR. is attained; depositing a layer of aluminum on said substrate by sputering with argon gas at said first sputtering pressure until said aluminum layer reaches a thickness of about 1 micron; depositing a layer of aluminum oxide on said aluminum layer by sputtering with an argon-oxygen gas mixture at a second pressure of about 1×10 -2 TORR. until said aluminum oxide layer attains a thickness of about 300 Angstroms; photolithographically patterning a resist such that said aluminum oxide layer provides increased absorption of light during photolithography; etching said aluminum and aluminum oxide layers, whereby said aluminum oxide layer reduces formation of mouse bites and notches on said aluminum layer; and annealing said semi-conductor chip whereby said aluminum oxide layer manifests reduced film stress.
Claim 12
Dependent Claim 23 words
The method of claim 9, wherein said aluminum oxide layer is formed in the presence of 94% argon gas and 6% oxygen gas.
Claim 13
Independent Claim 175 words
A method of forming a cap layer of aluminum oxide on an aluminum layer on a substrate for reducing film stress and the number of mouse bites and notches in said aluminum layer, comprising the steps of: depositing about a 1 micron thick layer of aluminum on said substrate, using an argon sputtering gas at a first pressure of about 6×10 -3 TORR. wherein deposition of said aluminum layer occurs at a rate of 1400 Å/min. using a power setting of 8.5 Kw; depositing about a 300 Angstrom thick layer of aluminum oxide on said aluminum layer by sputtering aluminum in the presence of argon and oxygen gas at a second pressure of about 1×10 -2 TORR., wherein deposition of said aluminum oxide layer occurs at a rate of 115 Å/min. using a power setting of 2.5 Kw; photolithographically patterning a resist such that said aluminum oxide layer provides increased absorption of light during patterning; and etching said layers wherein said aluminum oxide layer reduces formation of mouse bites and notches in said aluminum layer.
Claim 14
Independent Claim 175 words
A method of forming a cap layer of aluminum oxide on an aluminum layer on a substrate for reducing film stress and the number of mouse bites and notches in said aluminum layer, comprising the steps of: depositing about a 1 micron thick layer of aluminum on said substrate, using an argon sputtering gas at a first pressure of about 6×10 -3 TORR. wherein deposition of said aluminum layer occurs at a rate of 1400 Å/min. using a power setting of 8.5 Kw; depositing about a 300 Angstrom thick layer of aluminum oxide on said aluminum layer by sputtering aluminum in the presence of argon and oxygen gas at a second pressure of about 1×10 -2 TORR., wherein deposition of said aluminum oxide layer occurs at a rate of 115 Å/min. using a power setting of 2.5 Kw; photolithographically patterning a resist such that said aluminum oxide layer provides increased absorption of light during patterning; and etching said layers wherein said aluminum oxide layer reduces formation of mouse bites and notches in said aluminum layer.

References Cited (Backward Citations)

US3350222A Cited
US3355371A Cited
US4433004A Cited
US4302498A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-12-13 1992-06-13 1992-12-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-12-13 1996-06-13 1996-12-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-12-13 2000-06-13 2000-12-13 $7700.00 Window Closed / Lapsed

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