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US4789887A Expired / Lapsed US ⏱️ 0.0 years remaining

Controlling oscillator

Assignee: Skyworks Solutions Inc
•
Filing: 1986-09-29
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Granted: 1988-12-06
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Expires: 2006-09-29
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Abstract

Abstract A voltage controlled oscillator includes a VCO chip that is a monolithic circuit with a Gunn diode and varactor diode intercoupled by a resonant circuit. A detector/discriminator/power divider chip is coupled to the VCO chip through a directional coupler and is a monolithic circuit having a pair of discriminator diodes and amplitude detector diode on a semi-insulating substrate with associated circuit components. Connected-together electrodes of the discriminator diodes are connected to one output of the power divider. An electrode of the amplitude detector diode is connected to the other output of the power divider. Stagger-tuned resonant circuits are coupled to the other electrodes of the discriminator diodes. Conducting portions forming low pass filters couple the amplitude detector diode and the discriminator detector diodes to respective outputs. The outputs of the discriminator and amplitude detector are coupled to respective inputs of an analog divider that provides a ratio signal that is coupled to the - input of a differential amplifier. The + input of the differential amplifier receives a frequency designating potential. The output of the differential amplifier is coupled to the varactor diode.

Inventors

  • 👤 Ian Crossley
  • 👤 Daniel Donoghue
  • 👤 Robert Goldwasser
  • 👤 John Miley
  • 👤 Frank Spooner

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 15:26
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/02; H03L7/04

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 130 words
A monolithic circuit comprising, a semi-insulating substrate having a device side through which semiconductor devices may be diffused separated by said substrate from a circuit side carrying conductiong material forming circuits, said substrate having at least a first via opening extending between said device side and said circuit side of said substrate, said first via opening being filled with n+ material, a first n- layer on said device side covering said first via opening, a first ohmic contact on said n- layer coacting therewith to form a semiconductor device, and a portion of said conducting material on the circuit side of said device in contact with said n+ material in said first opening for establishing contact with said first semiconductor device through said n+ material in said first via opening.
Claim 2
Dependent Claim 130 words
A monolithic circuit comprising, a semi-insulating substrate having a device side through which semiconductor devices may be diffused separated by said substrate from a circuit side carrying conductiong material forming circuits, said substrate having at least a first via opening extending between said device side and said circuit side of said substrate, said first via opening being filled with n+ material, a first n- layer on said device side covering said first via opening, a first ohmic contact on said n- layer coacting therewith to form a semiconductor device, and a portion of said conducting material on the circuit side of said device in contact with said n+ material in said first opening for establishing contact with said first semiconductor device through said n+ material in said first via opening.
Claim 3
Dependent Claim 114 words
A monolithic circuit in accordance with claim 1 and further comprising, at least a second via opening in said substrate, said second via opening being filled with n+ material, a second n- layer in contact with said n+ material in said second via opening covering said second via opening on said device side, a second ohmic contact on said n- layer coacting therewith to form a second semiconductor device, a thermally and electrically conducting layer on said device side interconnecting said first and second ohmic contacts, and a second portion of said conducting material on said circuit side establishing contact with said second semiconductor device through the n+ material in said second via opening.

References Cited (Backward Citations)

US3617911A Cited
US3874918A Cited
US4028147A Cited
US4316201A Cited
US4374394A Cited
US4437109A Cited
US4507845A Cited
US4505799A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-12-06 1992-06-06 1992-12-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-12-06 1996-06-06 1996-12-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-12-06 2000-06-06 2000-12-06 $7700.00 Window Closed / Lapsed

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