US3874918A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Structure and process for semiconductor device using batch processing
Assignee: Motorola Solutions Inc
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Filing: 1974-02-19
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Granted: 1975-04-01
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Expires: 1994-02-19
Abstract
Abstract A fabrication process and structure for semiconductor devices allowing a large number of devices to be made utilizing batch processing techniques without individual handling of the devices. The process includes forming a plurality of mesas on a semiconductor wafer, each of which contains a semiconductor junction, coating the wafer with a thick glass coating, etching tapered holes in the glass over the mesas, and plating a contact onto the mesa filling the tapered holes. Diodes made according to the process display low capacitance and inductance, high reliablility and high power dissipation characteristics.
Inventors
- 👤 Marshall I Nechtow
- 👤 Jiri Sandera
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:27
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10D; H10D99/00; H10P; H10P54/00; H10W74/00; H10W74/10; H10W74/131
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
135 words
A METHOD OF FABRICATION OF SEMICONDUCTOR DEVICES WHICH COMPRISES THE STEPS OF: A. FORMING A SEMICONDUCTOR JUNCTION ON ONE SURFACE OF A WATER OF SEMICONDUCTOR MATERIAL; B. ETCHING AREAS OF SAID SURFACE OF SAID WAFER, EACH WHEREBY A PLURALITY OF MESAS ARE FORMED ON SAID WAFER, EACH OF SAID MESAS CONTAINING A SEMICONDUCTOR JUNCTION; C. COATING THE SIDE OF SAID WAFER CONTAINING SAID MESA WITH GLASS, THE THERMAL COEFFICIENT OF EXPANSION OF SAID GLASS BEING SUBSTANTIALLY THE SAME AS SAID WAFER; D. FORMING A MASK ON THE SURFACE OF SAID GLASS WHEREBY THE AREA OF SAID MESAS IS NOT COVERED BY SAID MASK; E. ETCHING SAID GLASS IN THE AREA NOT COVERED BY SAID MASK WHEREBY SUBSTANTIALLY CONICAL HOLES ARE ETCHED IN SAID GLASS OVER SAID MESAS; AND F. PLATING METAL IN SAID CONICAL HOLES.
Claim 2
Independent Claim
135 words
A METHOD OF FABRICATION OF SEMICONDUCTOR DEVICES WHICH COMPRISES THE STEPS OF: A. FORMING A SEMICONDUCTOR JUNCTION ON ONE SURFACE OF A WATER OF SEMICONDUCTOR MATERIAL; B. ETCHING AREAS OF SAID SURFACE OF SAID WAFER, EACH WHEREBY A PLURALITY OF MESAS ARE FORMED ON SAID WAFER, EACH OF SAID MESAS CONTAINING A SEMICONDUCTOR JUNCTION; C. COATING THE SIDE OF SAID WAFER CONTAINING SAID MESA WITH GLASS, THE THERMAL COEFFICIENT OF EXPANSION OF SAID GLASS BEING SUBSTANTIALLY THE SAME AS SAID WAFER; D. FORMING A MASK ON THE SURFACE OF SAID GLASS WHEREBY THE AREA OF SAID MESAS IS NOT COVERED BY SAID MASK; E. ETCHING SAID GLASS IN THE AREA NOT COVERED BY SAID MASK WHEREBY SUBSTANTIALLY CONICAL HOLES ARE ETCHED IN SAID GLASS OVER SAID MESAS; AND F. PLATING METAL IN SAID CONICAL HOLES.
Claim 3
Dependent Claim
21 words
The method of claim 1 where the thickness of said coating of glass is greater than the distance across said mesas.
Claim 4
Dependent Claim
27 words
The method of claim 1 and further including the step of depositing a layer of metal on the surface of said wafer opposite said coating of glass.
Claim 5
Dependent Claim
30 words
The method of claim 3 and further including the step of reducing the thickness of said wafer prior to depositing said layer of metal on the surface of said wafer.
Claim 6
Dependent Claim
12 words
The method of claim 4 where said metal is iron or nickel.
Claim 7
Independent Claim
81 words
The method of processing a semiconductor wafer which comprises the steps of: a. forming a plurality of mesas on one surface of said wafer, said mesas each containing a semiconductor junction; b. forming a coating of glass over said mesas; c. forming a plurality of tapered holes in said coating of glass whereby the top surface of said mesas is exposed; and d. plating metal in said tapered holes whereby ohmic contacts with the top surfaces of said mesas are made.
Claim 8
Independent Claim
81 words
The method of processing a semiconductor wafer which comprises the steps of: a. forming a plurality of mesas on one surface of said wafer, said mesas each containing a semiconductor junction; b. forming a coating of glass over said mesas; c. forming a plurality of tapered holes in said coating of glass whereby the top surface of said mesas is exposed; and d. plating metal in said tapered holes whereby ohmic contacts with the top surfaces of said mesas are made.
Claim 9
Dependent Claim
55 words
The method of claim 6 where said tapered holes are formed by a. masking the surface of said coating of glass, said mask having openings therein corresponding to said plurality of mesas; and b. applying acid to said coating of glass through said openings whereby tapered holes will be etched through said coating of glass.
Claim 10
Dependent Claim
18 words
The method of claim 7 where said coating of glass is thicker than the distance across said mesas.
Claim 11
Dependent Claim
28 words
The method of claim 8 and further including the step of cutting said wafer into a plurality of pieces, said pieces containing one or more of said mesas.
Claim 12
Independent Claim
113 words
The method of fabricating a plurality of diodes on a semiconductor wafer which comprises the steps of: a. forming a layer of semiconductor material on one surface of said wafer, said semiconductor material being of opposite conductivity type as said wafer; b. isolAting a plurality of areas of said layer of semiconductor material from each other by selectively removing portions of said layer of semiconductor material whereby a plurality of mesas are formed on said wafer; c. coating said wafer with a layer of glass; d. forming a plurality of tapered holes in said glass whereby said mesas are exposed; and e. plating an ohmic contact to said mesas through said tapered holes.
Claim 13
Independent Claim
113 words
The method of fabricating a plurality of diodes on a semiconductor wafer which comprises the steps of: a. forming a layer of semiconductor material on one surface of said wafer, said semiconductor material being of opposite conductivity type as said wafer; b. isolAting a plurality of areas of said layer of semiconductor material from each other by selectively removing portions of said layer of semiconductor material whereby a plurality of mesas are formed on said wafer; c. coating said wafer with a layer of glass; d. forming a plurality of tapered holes in said glass whereby said mesas are exposed; and e. plating an ohmic contact to said mesas through said tapered holes.
Claim 14
Dependent Claim
112 words
The process of fabricating a plurality of IMPATT diodes which comprises the steps of: a. epitaxially depositing a layer of moderate carrier concentration semiconductor material on a high carrier concentration semiconductor substrate of the same conductivity type material; b. diffusing a layer of high carrier concentration semiconductor material of opposite conductivity type into said epitaxial layer; c. selectively etching away said diffused layer and said epitaxial layer whereby a plurality of mesas are formed on said substrate; d. coating the surface of said substrate containing said mesas with glass; e. etching tapered holes in said glass whereby said mesas are exposed; and f. plating contacts on said mesas through said tapered holes.
Claim 15
Dependent Claim
112 words
The process of fabricating a plurality of IMPATT diodes which comprises the steps of: a. epitaxially depositing a layer of moderate carrier concentration semiconductor material on a high carrier concentration semiconductor substrate of the same conductivity type material; b. diffusing a layer of high carrier concentration semiconductor material of opposite conductivity type into said epitaxial layer; c. selectively etching away said diffused layer and said epitaxial layer whereby a plurality of mesas are formed on said substrate; d. coating the surface of said substrate containing said mesas with glass; e. etching tapered holes in said glass whereby said mesas are exposed; and f. plating contacts on said mesas through said tapered holes.
Claim 16
Dependent Claim
92 words
A diode which comprises: a. a substrate of first conductivity semiconductor material; b. a layer of second conductivity semiconductor material on one surface of said substrate, said layer covering only a portion of said surface; c. a layer of glass on said surface of said substrate, said layer of glass having an opening corresponding to the location of said layer of semiconductor material, said opening being larger at the surface of said layer of glass than at said layer of semiconductor material; and d. a plated metal contact substantially filling said opening.
Claim 17
Dependent Claim
92 words
A diode which comprises: a. a substrate of first conductivity semiconductor material; b. a layer of second conductivity semiconductor material on one surface of said substrate, said layer covering only a portion of said surface; c. a layer of glass on said surface of said substrate, said layer of glass having an opening corresponding to the location of said layer of semiconductor material, said opening being larger at the surface of said layer of glass than at said layer of semiconductor material; and d. a plated metal contact substantially filling said opening.
Claim 18
Dependent Claim
21 words
The diode of claim 12 where the thickness of said coating of glass is greater than the size of said mesas.
Claim 19
Dependent Claim
24 words
The diode of claim 13 and further including a layer of metal plated on the surface of said substrate opposite said coating of glass.
References Cited (Backward Citations)
US3632432A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-03-31 | 1978-09-30 | 1979-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-03-31 | 1982-09-30 | 1983-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-03-31 | 1986-09-30 | 1987-04-01 | $7700.00 | Window Closed / Lapsed |