Patent US4786831A successfully refreshed from Google Patents.
US4786831A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrating capacitively coupled transimpedance amplifier
Assignee: Raytheon Co
•
Filing: 1984-12-17
•
Granted: 1988-11-22
•
Expires: 2004-12-17
Abstract
Abstract An amplifier circuit 12 for an infrared detector 10 in a detector array formed on a large-scale integrated structure. The amplifier circuit is fabricated along with the detector on the structure and includes an amplifier stage capacitively coupled 14 to the detector 10 and an output stage. A switching FET 16 is provided to selectively couple the detector to an external biasing source and another switching FET 24 is provided to reset the amplifier stage after an integration period. In one embodiment the output stage 28 includes a storage capacitor 30 selectively coupled to the amplifier stage by a switching FET 32. In another embodiment the output encoding stage 28 includes a two-gate FET 32 to control the voltage on a storage capacitor 30. The two-gate FET controls a voltage source which periodically pulses and drains the capacitor. One FET gate is connected to the amplifier stage output and the other is connected to a clocking signal. In still another embodiment the output stage 128 includes a second capacitor 132 of smaller capacitance onto which a charge of the first capacitor 130 proportional to the output of the amplifier stage is placed for subsequent sampling.
Inventors
- 👤 Arthur L. Morse
- 👤 Steve D. Gaalema
- 👤 Ingrid M. Keimel
- 👤 Mary J. Hewitt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:00
CPC Classifications
H; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/15; H10F39/157; H10F39/1575; G; G01; G01J; G01J5/00; G01J5/10; G01J5/20; G01J5/22; G06; G06G; G06G7/00; G06G7/12; G06G7/18; G06G7/184; G06G7/186; G06G7/1865; H04; H04N; H04N25/00; H04N25/70; H04N25/76; H04N25/77; H04N25/78
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
108 words
An amplifier circuit for an infrared detector of a detector array fabricated on a large scale integrated structure, said amplifier circuit comprising: biasing means, separate from said detector, for biasing said detector, switching means, fabricated on said large scale integrated structure, connected between said biasing means and said detector, for selectively coupling said biasing means to said detector during a first time period and for decoupling said biasing means from said detector during a second time period, and amplifying means, connected to an output terminal of said detector, fabricated on said large scale integrated structure, for amplifying an output signal of said detector during said second time period.
Claim 2
Dependent Claim
108 words
An amplifier circuit for an infrared detector of a detector array fabricated on a large scale integrated structure, said amplifier circuit comprising: biasing means, separate from said detector, for biasing said detector, switching means, fabricated on said large scale integrated structure, connected between said biasing means and said detector, for selectively coupling said biasing means to said detector during a first time period and for decoupling said biasing means from said detector during a second time period, and amplifying means, connected to an output terminal of said detector, fabricated on said large scale integrated structure, for amplifying an output signal of said detector during said second time period.
Claim 3
Dependent Claim
35 words
The amplifier circuit of claim 1 further comprising a storage means, connected to an output terminal of said amplifying means, fabricated on said large scale integrated structure, for storing an output of said amplifying means.
Claim 4
Dependent Claim
49 words
The amplifier circuit of claim 2 further comprising switching means, connected between said storage means and said output terminal of said amplifying means, fabricated on said large scale integrated structure, for selectively coupling and decoupling said storage means to and from, respectively, an output terminal of said amplifying means.
Claim 5
Dependent Claim
46 words
The amplifier circuit of claim 3 wherein said switching means decouples said storage means from said output terminal of said amplifying means at a first time during said first time period and momentarily couples said storage means at a second time during said second time period.
Claim 6
Dependent Claim
154 words
An amplifier circuit for an infrared detector array fabricated on a large scale integrated structure, said amplifier circuit comprising: biasing means, separate from said detector, for biasing said detector, switching means, fabricated on said large scale integrated structure, connected between said biasing means and said detector, for selectively coupling said biasing means to said detector during a first time period and for decoupling said biasing means from said detector during a second time period, amplifying means, connected to an output terminal of said detector, fabricated on said large scale integrated structure, for amplifying an output signal of said detector during said second time period, and output means for providing a voltage proportional to an output signal of said amplifying means, connected to an output terminal of said amplifying means, comprising: a capacitive element; and voltage controlling means responsive to a voltage output of said amplifying means for controlling a voltage on said capacitive element.
Claim 7
Dependent Claim
154 words
An amplifier circuit for an infrared detector array fabricated on a large scale integrated structure, said amplifier circuit comprising: biasing means, separate from said detector, for biasing said detector, switching means, fabricated on said large scale integrated structure, connected between said biasing means and said detector, for selectively coupling said biasing means to said detector during a first time period and for decoupling said biasing means from said detector during a second time period, amplifying means, connected to an output terminal of said detector, fabricated on said large scale integrated structure, for amplifying an output signal of said detector during said second time period, and output means for providing a voltage proportional to an output signal of said amplifying means, connected to an output terminal of said amplifying means, comprising: a capacitive element; and voltage controlling means responsive to a voltage output of said amplifying means for controlling a voltage on said capacitive element.
Claim 8
Dependent Claim
64 words
The circuit of claim 5 wherein said voltage controlling means comprises an FET transistor having an enable gate and a voltage control input gate coupled to said output terminal of said amplifying means, said FET transistor being responsive to an enable signal at said enable gate for controlling said voltage on said capacitive element in accordance with said output signal of said amplifying means.
Claim 9
Dependent Claim
228 words
An amplifier circuit for an infrared detector array fabricated on a large scale integrated structure, said amplifier circuit comprising: biasing means, separate from said detector, for biasing said detector, switching means, fabricated on said large scale integrated structure, connected between said biasing means and said detector, for selectively coupling said biasing means to said detector during a first time period and for decoupling said biasing means from said detector during a second time period, amplifying means, connected to an output terminal of said detector, fabricated on said large scale integrated structure, for amplifying an output signal of said detector during said second time period, and output means for providing a voltage proportional to an output signal of said amplifying means, connected to an output terminal of said amplifying means, comprising: a first capacitive element, a second capacitive element having a capacitance less than that of said first capacitive element, charging means for periodically charging and draining said first and second capacitive elements, connected individually to said first and second capacitive elements, and transfer means, bridging said capacitive elements, for controlling the flow of charge between said first and second capacitive elements in accordance with said output signal of said amplifying means wherein a charge is stored on said first capacitive element proportional to said output signal of said amplifying means and then transfered to said second capacitive element.
Claim 10
Dependent Claim
228 words
An amplifier circuit for an infrared detector array fabricated on a large scale integrated structure, said amplifier circuit comprising: biasing means, separate from said detector, for biasing said detector, switching means, fabricated on said large scale integrated structure, connected between said biasing means and said detector, for selectively coupling said biasing means to said detector during a first time period and for decoupling said biasing means from said detector during a second time period, amplifying means, connected to an output terminal of said detector, fabricated on said large scale integrated structure, for amplifying an output signal of said detector during said second time period, and output means for providing a voltage proportional to an output signal of said amplifying means, connected to an output terminal of said amplifying means, comprising: a first capacitive element, a second capacitive element having a capacitance less than that of said first capacitive element, charging means for periodically charging and draining said first and second capacitive elements, connected individually to said first and second capacitive elements, and transfer means, bridging said capacitive elements, for controlling the flow of charge between said first and second capacitive elements in accordance with said output signal of said amplifying means wherein a charge is stored on said first capacitive element proportional to said output signal of said amplifying means and then transfered to said second capacitive element.
Claim 11
Dependent Claim
71 words
The circuit of claim 7 wherein said transfer means comprises an FET transistor having an enable gate and a voltage control input gate coupled to said output terminal of said amplifying means, said FET transistor being responsive to an enable signal at said enable gate for controlling a transfer of charge from said first capacitive element to said second capacitive element in accordance with said output signal of said amplifying means.
References Cited (Backward Citations)
US3636458A
Cited
US3868580A
Cited
US4075576A
Cited
SU739549A1
Cited
US4313067A
Cited
US4439693A
Cited
US4578646A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-22 | 1992-05-23 | 1992-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-22 | 1996-05-23 | 1996-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-22 | 2000-05-23 | 2000-11-22 | $7700.00 | Window Closed / Lapsed |