Patent US4783845A successfully refreshed from Google Patents.
US4783845A
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US
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Digital tone squelch detector
Assignee: ITT AEROSPACE OPTICAL
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Filing: 1985-12-20
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Granted: 1988-11-08
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Expires: 2005-12-20
Abstract
Abstract A digital tone squelch detect circuit functions to give an enabling signal for audio transmission in an FM radio network. The circuit comprises an analog to digital converter which outputs a binary coded signal representative of the voltage level of a received audio tone signal. The binary signal is then placed into a shift register which periodically is rotated and multiplied by a reference clock signal for correlation with a stored replica of the tone. The output of the correlator, which is representative of the degree of correlation, is fed to an accumulator which integrates it and sends it to a comparator where its binary valve is compared to an arbitrary threshold binary value by a hysteresis network. After detection the hysteresis established circuit outputs a tone detect signal and lowers the detection threshold so as to maintain the tone detect signal during periods of signal fadeout. However, if no signal is detected for several cycles, the threshold is raised to the previous binary level so as to avoid triggering on noise.
Inventors
- 👤 James R. McChesney
- 👤 Michael W. Cook
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 19:07
CPC Classifications
H; H04; H04W; H04W88/00; H04W88/02; H04W88/022; H04W88/025; H04W88/027
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
175 words
A digital tone squelch circuit comprising: means for converting a first received analog signal to a first digital signal based on the amplitude of the first received analog signal; means for correlating said first digital signal with a stored signal proportional to said first digital signal to generate a second digital signal based on the correlation between said first digital signal and said stored signal; comparator means for comparing said second digital signal with a threshold signal whereby the presence of said first analog signal can be established; a shift register connected to receive an output from said means for converting and provide an input to said means for correlating; and a clock generator connected to said shift register to rotate the contents of said shift register with a signal of a first frequency and also connected to said means for correlating with a signal of such a second frequency that the signal from said shift register to said means for correlating is effectively compared against a stored replica of said first received analog signal.
Claim 2
Dependent Claim
175 words
A digital tone squelch circuit comprising: means for converting a first received analog signal to a first digital signal based on the amplitude of the first received analog signal; means for correlating said first digital signal with a stored signal proportional to said first digital signal to generate a second digital signal based on the correlation between said first digital signal and said stored signal; comparator means for comparing said second digital signal with a threshold signal whereby the presence of said first analog signal can be established; a shift register connected to receive an output from said means for converting and provide an input to said means for correlating; and a clock generator connected to said shift register to rotate the contents of said shift register with a signal of a first frequency and also connected to said means for correlating with a signal of such a second frequency that the signal from said shift register to said means for correlating is effectively compared against a stored replica of said first received analog signal.
Claim 3
Dependent Claim
212 words
A digital tone squelch circuit comprising: means for converting a first received analog signal to a first digital signal based on the amplitude of the first received analog signal; means for correlating said first digital signal with a stored signal proportional to said first digital signal to generate a second digital signal based on the correlation between said first digital signal and said stored signal; comparator means for comparing said second digital signal with a threshold signal whereby the presence of said first analog signal can be established; a shift register connected to receive an output from said means for converting and provide an input to said means for correlating; said means for converting a first received analog signal to a first digital signal produces a 3 bit digital signal; wherein said shift register is 64×3 bit digital shift register and an output signal from said shift register is multiplied by a signal from a reference clock upon rotation of said shift register to provide a first correlator input signal to a first input of said means for correlating; and said reference clock provides a second correlator input signal to a second input of said means for correlating whereupon said means for correlating provides at an output thereof said second digital signal.
Claim 4
Dependent Claim
212 words
A digital tone squelch circuit comprising: means for converting a first received analog signal to a first digital signal based on the amplitude of the first received analog signal; means for correlating said first digital signal with a stored signal proportional to said first digital signal to generate a second digital signal based on the correlation between said first digital signal and said stored signal; comparator means for comparing said second digital signal with a threshold signal whereby the presence of said first analog signal can be established; a shift register connected to receive an output from said means for converting and provide an input to said means for correlating; said means for converting a first received analog signal to a first digital signal produces a 3 bit digital signal; wherein said shift register is 64×3 bit digital shift register and an output signal from said shift register is multiplied by a signal from a reference clock upon rotation of said shift register to provide a first correlator input signal to a first input of said means for correlating; and said reference clock provides a second correlator input signal to a second input of said means for correlating whereupon said means for correlating provides at an output thereof said second digital signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-08 | 1992-05-09 | 1992-11-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-08 | 1996-05-09 | 1996-11-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-08 | 2000-05-09 | 2000-11-08 | $7700.00 | Window Closed / Lapsed |