Abstract A squelch circuit in which a phase locked loop (PLL) (5) having a voltage controlled oscillator (VCO) (7) and a phase comparator (10) is used to detect the number of zero crossings, these being low for a speech signal and high for noise. The error voltage produced in the phase locked loop (5) is fed through a network (12) which ensures that the matching of the input signal to the oscillator is faster when the input frequency drops than when the input frequency rises. The input signal is clipped to enhance the frequency spectra of speech by using a limiting amplifier. The muting gate (2) output is derived from the VCO (7) control voltage of the PLL (5) to mute the output of the receiver when the VCO (7) output frequency is higher than a pre-set frequency for more than a pre-set time.
A squelch circuit for muting audio output of a receiver except when a desired audio signal is received, comprising: an input terminal connected to a limiting amplifier and a muting gate; a phase locked loop which receives the limiting amplifier output and which contains an oscillator and a phase comparator for comparing the frequency of said oscillator and said limiting amplifier output to produce an error voltage which is fed back to control said oscillator through a network to enable the oscillator to match its frequency to that of the limiting amplifier output, the match occurring faster when the limiting amplifier output frequency drops than when the limiting amplifier output frequency rises; said muting gate being coupled to an output of said network to mute the output of the receiver when the limiting amplifier output frequency is higher than that desired.
Claim 2
Dependent Claim
141 words
A squelch circuit for muting audio output of a receiver except when a desired audio signal is received, comprising: an input terminal connected to a limiting amplifier and a muting gate; a phase locked loop which receives the limiting amplifier output and which contains an oscillator and a phase comparator for comparing the frequency of said oscillator and said limiting amplifier output to produce an error voltage which is fed back to control said oscillator through a network to enable the oscillator to match its frequency to that of the limiting amplifier output, the match occurring faster when the limiting amplifier output frequency drops than when the limiting amplifier output frequency rises; said muting gate being coupled to an output of said network to mute the output of the receiver when the limiting amplifier output frequency is higher than that desired.
Claim 3
Dependent Claim
20 words
A squelch circuit as claimed in claim 1 in which the limiting amplifier enchances the dominant frequency spectra of speech.