Process for fabricating a bipolar transistor utilizing sidewall masking over the emitter

Claim 2

A process for fabricating a semiconductor integrated circuit device comprising: (a) a step of selectively oxidizing a polysilicon layer deposited on the working surface of a silicon substrate; (b) a step of partially removing the polysilicon oxide layer to form an opening; (c) a step of forming a chemical vapor deposition layer on the entire surface; and (d) a step of anisotropic etching of said chemical vapor deposition layer to leave the chemical vapor deposition layer on the sidewall of the opening.

Claim 3

A process as set forth in claim 1, further comprising: (e) a step of forming an emitter window using the chemical vapor deposition layer as a mask.

Claim 4

A process as set forth in claim 2, wherein the chemical vapor deposition layer is a compound layer comprising a silicon nitride layer or a polysilicon layer on a silicon oxide layer.

Claim 5

A process for fabricating a semiconductor integrated circuit device comprising: (a) a first step of depositing polysilicon on a silicon substrate having an island region of a first conduction type on its working surface, and of forming an oxidationresistant film on selected areas of this polysilicon; (b) a second step of selectively oxidizing the polysilicon, and introducing an impurity of a second conduction type into the remaining polysilicon through the oxidation-resistant film; (c) a third step of selectively removing a portion of the polysilicon oxide film to form an opening exposing part of the island region; (d) a fourth step of forming a thin oxide film on the exposed island region and its polysilicon sidewalls, and of forming a first region of the second conduction type in the unexposed island regions; (e) a fifth step of introducing an impurity of the second conduction type into said island region through said thin oxide film, and of forming a second region of the second conduction type adjacent to the first region; (f) a sixth step of forming a chemical vapor deposition layer on the entire surface and performing anisotropic etching to leave the chemical vapor deposition layer on the sidewall of the opening; (g) a seventh step of etching sid thin oxide film using the remaininng chemical vapor deposition layer as a mask, and exposing the surface of the second region; and (h) an eighth step of forming a third region of the first conduction type, using the impurity of the first conduction type from the exposed surface of the second region.

Claim 6

A process for fabricating a semiconductor integrated circuit device comprising: (a) a first step of depositing polysilicon on a silicon substrate having an island region of a first conduction type on its working surface, and of forming an oxidationresistant film on selected areas of this polysilicon; (b) a second step of selectively oxidizing the polysilicon, and introducing an impurity of a second conduction type into the remaining polysilicon through the oxidation-resistant film; (c) a third step of selectively removing a portion of the polysilicon oxide film to form an opening exposing part of the island region; (d) a fourth step of forming a thin oxide film on the exposed island region and its polysilicon sidewalls, and of forming a first region of the second conduction type in the unexposed island regions; (e) a fifth step of introducing an impurity of the second conduction type into said island region through said thin oxide film, and of forming a second region of the second conduction type adjacent to the first region; (f) a sixth step of forming a chemical vapor deposition layer on the entire surface and performing anisotropic etching to leave the chemical vapor deposition layer on the sidewall of the opening; (g) a seventh step of etching sid thin oxide film using the remaininng chemical vapor deposition layer as a mask, and exposing the surface of the second region; and (h) an eighth step of forming a third region of the first conduction type, using the impurity of the first conduction type from the exposed surface of the second region.

Claim 7

A process as set forth in in claim 4, wherein the chemical vapor deposition layer is a compound layer comprising a silicon nitride layer or a polysilicon layer on a silicon oxide layer.

Claim 8

A process as set forth in claim 4, wherein the first conduction type is the N type, the second conduction type is the P type, the impurity of the first conduction type is arsenic, and the impurity of the second conduction type is boron.