Patent US4782253A successfully refreshed from Google Patents.
US4782253A
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High speed MOS circuits
Assignee: Nokia Bell Labs
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Filing: 1987-09-21
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Granted: 1988-11-01
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Expires: 2007-09-21
Abstract
Abstract Integrated circuit chips with two (or more) multi-element logic paths-suffering from signal skew operation because of semiconductor processing variations-can be made to exhibit substantially reduced skew by designing the elements such that the sum of the pull-up delays in one logic path is approximately equal to the sum of the pull-up delays in the other logic path (or in each of the other logic paths) and such that the sum of all the delays (pull-down plus pull-up) in one path is substantially equal to the sum of all the delays in (each of) the other(s)-all in response to an input signal transition (low to high, high to low, or both) applied to each path.
Inventors
- 👤 Masakazu Shoji
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:00
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/151; H10; H10D; H10D89/00; H10D89/10
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
186 words
An integrated circuit chip including first and second logic paths to which electrical signals are to be applied simultaneously, said first and second paths composed respectively of a plurality of logic elements characterized by high input impedance and connected in cascade, each of such elements having a characteristic pull-up and a characteristic pull-down delay, wherein in response to a rising input signal transition applied to an input end of each of the first and second paths the sum of the pull-down delays of the elements in said first path that pull-down their respective outputs in response thereto substantially equals the sum of the pull-down delays of the elements in said second path that pull-down their respective outputs in response thereto and in response to a falling input signal transition applied to the input end of each of the first and second paths the sum of the pull-up delays of the elements in said first path that pull-up their respective outputs in response thereto substantially equals the sum of the pull-up delays of the elements in said second path that pull-up their respective outputs in response thereto.
Claim 2
Dependent Claim
186 words
An integrated circuit chip including first and second logic paths to which electrical signals are to be applied simultaneously, said first and second paths composed respectively of a plurality of logic elements characterized by high input impedance and connected in cascade, each of such elements having a characteristic pull-up and a characteristic pull-down delay, wherein in response to a rising input signal transition applied to an input end of each of the first and second paths the sum of the pull-down delays of the elements in said first path that pull-down their respective outputs in response thereto substantially equals the sum of the pull-down delays of the elements in said second path that pull-down their respective outputs in response thereto and in response to a falling input signal transition applied to the input end of each of the first and second paths the sum of the pull-up delays of the elements in said first path that pull-up their respective outputs in response thereto substantially equals the sum of the pull-up delays of the elements in said second path that pull-up their respective outputs in response thereto.
Claim 3
Dependent Claim
98 words
An integrated circuit chip in accordance with claim 1 wherein each of said elements in said first and second paths comprise one or more transistors and wherein the widths of said transistors in said elements in said first and second paths are selected so that the said sum of the said pull-down delays in the first path substantially equals the said sum of the said pull-down delays in the second path and the said sum of the said pull-up delays in the first path substantially equals the said sum of the said pull-up delays in the second path.
Claim 4
Dependent Claim
22 words
An integrated circuit chip in accordance with claim 2 wherein the numbers of elements in said first and second paths are different.
Claim 5
Dependent Claim
34 words
An integrated circuit chip in accordance with claim 3 wherein all said pull-up and all said pull-down transistors are PFETs and NFETs, respectively, which formed during different first and second semiconductor processing operations, respectively.
Claim 6
Dependent Claim
123 words
An integrated circuit chip comprising at least two logic paths to each of which electrical signals are to be applied simultaneously, said paths having differing respective numbers of logic elements connected in cascade, each of said elements having either a pull-up delay or a pull-down delay in response to an input signal applied to the paths, such that in response to a rising input signal the sums of the pull-down delays of those logic elements which pull-down their respective outputs in response thereto in each path are substantially equal and such that in response to a falling input signal the sums of the pull-up delays of those logic elements which pull-up their respective outputs in response thereto in each path are substantially equal.
Claim 7
Dependent Claim
123 words
An integrated circuit chip comprising at least two logic paths to each of which electrical signals are to be applied simultaneously, said paths having differing respective numbers of logic elements connected in cascade, each of said elements having either a pull-up delay or a pull-down delay in response to an input signal applied to the paths, such that in response to a rising input signal the sums of the pull-down delays of those logic elements which pull-down their respective outputs in response thereto in each path are substantially equal and such that in response to a falling input signal the sums of the pull-up delays of those logic elements which pull-up their respective outputs in response thereto in each path are substantially equal.
Claim 8
Dependent Claim
17 words
An integrated circuit chip in accordance with claim 5 wherein said electrical signal is a clock signal.
Claim 9
Dependent Claim
21 words
An integrated circuit chip in accordance with claim 5 wherein each of said logic elements is essentially a complementary-metal-oxide-semiconductor (CMOS) inverter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1991-11-01 | 1992-05-02 | 1992-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-01 | 1996-05-02 | 1996-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-01 | 2000-05-02 | 2000-11-01 | $7700.00 | Window Closed / Lapsed |