High density, dynamic, content-addressable memory cell

Claim 2

A content-addressable memory cell, having four signal lines, comprising: a random access memory cell coupled to a bit line and to a word line wherein said random access memory cell comprises a first metal-oxide-semiconductor field effect transistor; an exclusive-NOR gate coupled to said cell and to said bit line and coupling said cell to a match signal line and to a mask signal line; and wherein said exclusive-NOR gate further comprises: two pairs of complementary metal-oxide-semiconductor field effect transistors; said first pair having a second transistor having a first source/drain terminal coupled to one of said mask lines, a gate terminal coupled to said bit line, and a second source/drain terminal coupled to said other transistor of said first pair, and a third transistor having a third source/drain terminal coupled to said second source/drain terminal, a gate terminal coupled to said cell transistor-second source/drain terminal, and a fourth source/drain terminal coupled to the second of said mash lines; and said second pair having a fourth transistor having a fifth source/drain terminal coupled to said same one of said mask lines as said second transistor, a gate terminal coupled to said bit line, and a sixth source/drain terminal coupled to the other transistor of said second pair, and a fifth transistor having a seventh source/drain terminal coupled to said sixth source/drain terminal, a gate terminal coupled to said cell transistor-second source/drain terminal, and an eighth source/drain terminal coupled to the second of said mask lines.

Claim 3

The memory cell as set forth in claim 1, wherein said exclusive-NOR gate implements a Boolean equation comprising: A XNOR B=(/A·/B)+(A·B), where A and B are input variables.

Claim 4

The memory cell as set forth in claim 2, wherein said input variables comprise: a signal from said bit line; and a signal from said random access memory cell.

Claim 5

The memory cell as set forth in claim 1, further comprising: said first transistor having a first source/drain terminal coupled to said bit line, a second source/drain terminal coupled to said exclusive-NOR gate, and a gate coupled to said word line.

Claim 6

The memory cell as set forth in claim 1, further comprising: a capacitor having a first terminal coupled to said second source/drain terminal, and a second terminal coupled to a circuit reference potential level.

Claim 7

The memory cell as set forth in claim 1, wherein said memory cell further comprises: the gate region of said third transistor.

Claim 8

The memory cell as set forth in claim 1, further comprising: said first, third and fourth transistors are n-channel type; and said second and fifth transistors are p-channel type.

Claim 9

An improved content-addressable memory, having a matrix array of signal lines having a plurality, m, of bit lines and a plurality, n, of word lines, and a plurality, n, of match lines and a plurality, m, of mask lines, and having a plurality of memory cells coupling said signal lines, characterized in that said memory cells each comprise: a random access memory component coupled to one of said bit lines and one of said work lines wherein said random access memory component comprises a first metal-oxide-semiconductor field effect transistor, said first transistor having a first source/drain terminal coupled to said bit line, a second source/drain terminal coupled to said exclusive-NOR gate, and a gate coupled to said word line; a capacitor having a first terminal coupled to said second source/drain terminal, and a second terminal coupled to a cicuit reference potential level; and an exclusive-NOR gate, having a first input coupled to said bit line and a second input coupled to said memory component and a comparison input coupled to one of said mask lines and an output coupled to one of said match lines, wherein said exclusive-NOR gate further comprises: two pairs of complementary metal-oxide-semiconductor field effect transistors; said first pair having a second transistor having a first source/drain terminal coupled to one of said mask lines, a gate terminal coupled to said bit line, and a second source/drain terminal coupled to said other transistor of said first pair, and a third transistor having a third source/drain terminal coupled to said second source/drain terminal, a gate terminal coupled to said cell transistor-second source/drain terminal, and a fourth source/drain terminal coupled to the second of said mask lines; and said second pair having a fourth transistor having a fifth source/drain terminal coupled to said same one of said mask lines as said second transistor, a gate terminal coupled to said bit line, and a sixth source/drain terminal coupled to the other transistor of said second pair, and a fifth transistor having a seventh source/drain terminal coupled to said sixth source/drain terminal, a gate terminal coupled to said cell transistor-second source/drain terminal, and an eighth source/drain terminal coupled to the second of said mask lines.

Claim 10

An improved content-addressable memory, having a matrix array of signal lines having a plurality, m, of bit lines and a plurality, n, of word lines, and a plurality, n, of match lines and a plurality, m, of mask lines, and having a plurality of memory cells coupling said signal lines, characterized in that said memory cells each comprise: a random access memory component coupled to one of said bit lines and one of said work lines wherein said random access memory component comprises a first metal-oxide-semiconductor field effect transistor, said first transistor having a first source/drain terminal coupled to said bit line, a second source/drain terminal coupled to said exclusive-NOR gate, and a gate coupled to said word line; a capacitor having a first terminal coupled to said second source/drain terminal, and a second terminal coupled to a cicuit reference potential level; and an exclusive-NOR gate, having a first input coupled to said bit line and a second input coupled to said memory component and a comparison input coupled to one of said mask lines and an output coupled to one of said match lines, wherein said exclusive-NOR gate further comprises: two pairs of complementary metal-oxide-semiconductor field effect transistors; said first pair having a second transistor having a first source/drain terminal coupled to one of said mask lines, a gate terminal coupled to said bit line, and a second source/drain terminal coupled to said other transistor of said first pair, and a third transistor having a third source/drain terminal coupled to said second source/drain terminal, a gate terminal coupled to said cell transistor-second source/drain terminal, and a fourth source/drain terminal coupled to the second of said mask lines; and said second pair having a fourth transistor having a fifth source/drain terminal coupled to said same one of said mask lines as said second transistor, a gate terminal coupled to said bit line, and a sixth source/drain terminal coupled to the other transistor of said second pair, and a fifth transistor having a seventh source/drain terminal coupled to said sixth source/drain terminal, a gate terminal coupled to said cell transistor-second source/drain terminal, and an eighth source/drain terminal coupled to the second of said mask lines.

Claim 11

The memory cell as set forth in claim 8, wherein said exclusive-NOR gate implements a Boolean equation comprising: A XNOR B=(/A·B)+(A·B), where A and B are input variables.

Claim 12

The memory cell as set forth in claim 9, wherein said input variables comprise: a signal from said bit line; and a signal from said random access memory cell.

Claim 13

The memory cell as set forth in claim 8, wherein said memory component further comprises: the gate region of said third transistor.

Claim 14

The memory cell as set forth in claim 8, further comprising: said first, third and fourth transistors are n-channel types; and said second and fifth transistors are p-channel types.