Associative memory with improved memory cell and method for operating same

Claim 1

An associative memory having a plurality of memory cells arranged in i rows, each row having j cells for use with i word lines respectively for said rows, j bit lines and j complementary bit lines respectively for each of said cells, and at least one hit line, each said memory cell comprising: a random access memory cell having first and second output terminals; a pair of first transistors each having a control electrode connected to the word line for the row in which said cell is located and one of said first transistors being interconnected between said first terminal of said random access memory cell and the bit line for said cell and the other of said first transistors being interconnected between said second terminal of said random access memory cell and the complementary bit line for said cell; a pair of second transistors having a common terminal, one of said second transistors having a control electrode connected to said first terminal of said random access memory cell and being connected to said complementary bit line for said cell and the other of said second transistors having a control electrode connected to said second terminal of said random access memory cell and being connected to said bit line for said cell; a third transistor connected to said hit line and having a control electrode connected to said common terminal of said second transistors, and said associative memory further having i load transistors each having a current path connected between a supply voltage and said hit line and a control electrode for said current path also connected to said hit line, each said load transistor forming a NOR gate in combination with said third transistors of each said cell in a row whereby information on said bit line is written into said random access memory cell when said word line activated and information on said bit line is compared with information stored in said random access memory cell when said word line is non-activated and the result of said comparison is utilized for controlling said third transistor for enabling of inhibiting said hit line.

Claim 5

A method for operating an associative memory having a plurality of RAM cells disposed in rows and columns, each cell having output terminals respectively connected through transistors, which are controlled by a word line for the row containing the cell, to a bit line and a complementary bit line and which terminals are further cross-connected to control electrodes of additional transistors connected to said bit line and said complementary bit line and having a common terminal connected to the control electrode of a transistor for determining the status of a hit line, comprising the steps of: writing information into one of said RAM cells from said bit line only when the word line for the row containing the cell is activated; comparing a specific word on said bit line in parallel with all words stored in all of said RAM cells in the row connected to the activated word line after activation thereof; and setting the status of said hit line in dependence upon the results of said comparison by switching said transistor for determining the status of said hit line.

Claim 6

A method for operating an associative memory having a plurality of RAM cells disposed in rows and columns, each cell having output terminals respectively connected through transistors, which are controlled by a word line for the row containing the cell, to a bit line and a complementary bit line and which terminals are further cross-connected to control electrodes of additional transistors connected to said bit line and said complementary bit line and having a common terminal connected to the control electrode of a transistor for determining the status of a hit line, comprising the steps of: writing information into one of said RAM cells from said bit line only when the word line for the row containing the cell is activated; comparing a specific word on said bit line in parallel with all words stored in all of said RAM cells in the row connected to the activated word line after activation thereof; and setting the status of said hit line in dependence upon the results of said comparison by switching said transistor for determining the status of said hit line.