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US4780820A Expired / Lapsed US ⏱️ 0.0 years remaining

Control flow computer using mode and node driving registers for dynamically switching between parallel processing and emulation of von neuman processors

Assignee: Individual
•
Filing: 1987-03-09
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Granted: 1988-10-25
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Expires: 2007-03-09
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Abstract

Abstract A parallel processing computer comprises at least a memory for storing program as well as data and instructions for executing the program, a plurality of functional units, a node driving register for indicating executable instructions which are allowed to be executed by the functional units, and a mode register giving information to the functional unit as to whether the processing to be executed is of serial nature or parallel nature.

Inventors

  • 👤 Masahiro Sowa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 09:05
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/44; G06F9/448; G06F9/4494

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 217 words
A parallel processing computer comprising: a plurality of functional units (FU 1 . . . FU n ) for executing instructions in parallel with one another; a memory (4) for storing said instructions and data to be utilized in execution of said instructions by said functional units; a node driving register (1) for indicating instructions to be executed in parallel by said functional units, respectively; a mode register means (2) connected to said functional units for storing information indicative of either a serial and parallel operation mode of said functional units; and wherein said node driving register includes a plurality of node pointers, for serving as the program counter in a Von-Neuman processing operation, each of said node pointers (NPR) constituted by at least one word of said node driving register (1) designated by a given one of said functional units (FU 1 , . . . , FU n ) connected with said mode register means, which is loaded with serial operation mode information and temporarily allocated for use only by said given one functional unit, to thereby serve as a program counter for a serial type operation of said given functional unit so that a serial type program is executed by said given one functional unit in cooperation with a node pointer and said memory.
Claim 2
Dependent Claim 217 words
A parallel processing computer comprising: a plurality of functional units (FU 1 . . . FU n ) for executing instructions in parallel with one another; a memory (4) for storing said instructions and data to be utilized in execution of said instructions by said functional units; a node driving register (1) for indicating instructions to be executed in parallel by said functional units, respectively; a mode register means (2) connected to said functional units for storing information indicative of either a serial and parallel operation mode of said functional units; and wherein said node driving register includes a plurality of node pointers, for serving as the program counter in a Von-Neuman processing operation, each of said node pointers (NPR) constituted by at least one word of said node driving register (1) designated by a given one of said functional units (FU 1 , . . . , FU n ) connected with said mode register means, which is loaded with serial operation mode information and temporarily allocated for use only by said given one functional unit, to thereby serve as a program counter for a serial type operation of said given functional unit so that a serial type program is executed by said given one functional unit in cooperation with a node pointer and said memory.
Claim 3
Dependent Claim 76 words
A parallel processing computer as set forth in claim 1, said mode register means includes a plurality of mode registers (MD 1 , . . . , MD n ) each connected to one of said plurality of function units (FU 1 , . . . , FU n ), respectively, each mode register storing information indicative of either a parallel or serial operation mode in which the respective functional units are to execute respective instructions.
Claim 4
Dependent Claim 30 words
A parallel processing computer as set forth in claim 1, wherein execution of instruction is controlled by a token which simultaneously represents data to be used in executing said instruction.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-10-25 1992-04-25 1992-10-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-10-25 1996-04-25 1996-10-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-10-25 2000-04-25 2000-10-25 $7700.00 Window Closed / Lapsed

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