Testing programmable logic arrays

Claim 1

A programmable logic array comprising a plurality of data bit lines selectively coupled to a plurality of product lines which are in turn selectively coupled to a plurality of output lines, a plurality of address bit lines selectively coupled to the product lines to form an integral decoder allowing individual product lines to be selected, sequencing means for applying a sequence of addresses to the address bit lines to select each product line in turn, and buffer means operable to disable all the address bit lines so as to prevent them having any effect on the product lines, characterised by a further product line and a further output line, the further product line being connected to all the address bit lines and to the further output line, but not to any of the other output lines, and the further output line being connected to the further product line but not to any of the other product lines, whereby faults in the buffer means preventing them from disabling the address bit lines can be detected by observation of output signals on the further output line.