Forced error generating circuit for a data processing unit

Claim 1

A forced error generating circuit for a data processing unit comprising: a forced error register for generating a designation signal to forcibly cause an error for a structural element in the data processing unit; and a signal generating means which receives a signal for starting a period for causing the error by way of an internal forced error generating instruction and generates a forced error generating signal corresponding to said designation signal during said period, wherein said signal for starting the period for forcibly causing error is an instruction starting signal, and wherein said generating means includes a forced error controlling circuit for generating a forced error generating instruction A signal in the last machine cycle of said forced error generating instruction, a first circuit for generating a forced error generating instruction B signal by latching said forced error generating instruction A signal in said last machine cycle and a second circuit for latching a forced error controlling B signal in response to said instruction starting signal, in the period of an instruction I subsequent to said forced error generating instruction when a forced error controlling A signal in synchronism with said forced error generating instruction B signal is generated from said forced error controlling circuit, whereby said forced error controlling circuit generates said forced error generating signal in response to said forced error controlling B signal.