Patent US4779060A successfully refreshed from Google Patents.
US4779060A
Expired / Lapsed
US
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Linear power amplifying system
Assignee: Teledyne Technologies Inc
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Filing: 1987-06-01
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Granted: 1988-10-18
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Expires: 2007-06-01
Abstract
Abstract A power MOSFET linear amplifier includes a plurality of paralleled MOSFETS having a gate-to-source resistor to ensure simultaneous turn-on and sharing of the load current. An arc lamp is connected in series with a 400 volt power supply and a variable ballast element in the form of the power MOSFET linear amplifier. The linear amplifier includes four similar modules. Each module is a hybrid circuit constructed with eight MOSFETs connected in parallel. Each MOSFET includes a similar gate-to-source resistor in addition to an appropriate gate resistor and source resistor. Under operating load current conditions, the gate-to-source resistors are laser trimmed to establish precise equalized current sharing in response to the specified operating input voltages. The module is set with the gate voltage slightly above the operating threshold voltage range of the MOSFET. The modules then operate with the essentially simultaneous turn-on of all MOSFETs and in a reliable balancing of current between the several MOSFET devices. The modules are fabricated with a common heat sink and an appropriate packaging for rapid dissipation of the heat, to thereby maintain the necessary low operating temperature which is essential to reliable operation of the MOSFET devices.
Inventors
- 👤 James Henden
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:21
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/20; H03F3/21; H03F3/211
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
124 words
A power MOSFET linear amplifier, comprising: a plurality of MOSFET devices connected in parallel, each of said devices having a drain terminal and a source terminal connected in series with a source resistor and a gate terminal connected in series with a gate resistor and having a gate-to-source resistance, a common drain line connected to each of said drain terminals, a common source line connected to said source resistors, a balancing resistor connecting said gate terminal to said source terminal, and said balancing resistors each having a resistance related to the internal gate-to-source resistance to establish essentially equal threshold voltages for the several units and thereby establish equal distribution of the total current flow between said common source line and said common drain line.
Claim 2
Dependent Claim
124 words
A power MOSFET linear amplifier, comprising: a plurality of MOSFET devices connected in parallel, each of said devices having a drain terminal and a source terminal connected in series with a source resistor and a gate terminal connected in series with a gate resistor and having a gate-to-source resistance, a common drain line connected to each of said drain terminals, a common source line connected to said source resistors, a balancing resistor connecting said gate terminal to said source terminal, and said balancing resistors each having a resistance related to the internal gate-to-source resistance to establish essentially equal threshold voltages for the several units and thereby establish equal distribution of the total current flow between said common source line and said common drain line.
Claim 3
Dependent Claim
53 words
The linear amplifier of claim 1 including an insulating substrate, said resistors being deposited as thick film resistors and said devices being affixed on said substrate to form an integrated hybrid circuit, said balancing resistors being laser trimmed under predetermined load current conditions to establish said equal distribution of the total current flow.
Claim 4
Dependent Claim
31 words
The power amplifier of claim 1 wherein said source resistors are each essentially one ohm two percent resistors and said drain resistors are each essentially two hundred ohms five percent resistors.
Claim 5
Independent Claim
169 words
The method of making a power MOSFET linear amplifier for operating at a high voltage and low current and having a stable temperature coefficient at said low current, comprising: connecting a plurality MOSFET devices in parallel circuit configuration including at least one of said devices in each of a plurality of paralleled branch circuits, each of said MOSFED devices having a gate means and a drain means and a source means, load terminal means connected to said drain means and said source means, a control terminal means connected to said gate means, and a balancing resistance means connected between said gate means and said source means, connecting said load terminal means in circuit with a power supply to establish a selected drain current, connecting said control terminal means to an electrical control signal means for establishing said drain current, and trimming said balancing resistance means under conditions of said drain current to establish essentially equal turn-on of said devices and thereby load current flow in each of said devices.
Claim 6
Independent Claim
169 words
The method of making a power MOSFET linear amplifier for operating at a high voltage and low current and having a stable temperature coefficient at said low current, comprising: connecting a plurality MOSFET devices in parallel circuit configuration including at least one of said devices in each of a plurality of paralleled branch circuits, each of said MOSFED devices having a gate means and a drain means and a source means, load terminal means connected to said drain means and said source means, a control terminal means connected to said gate means, and a balancing resistance means connected between said gate means and said source means, connecting said load terminal means in circuit with a power supply to establish a selected drain current, connecting said control terminal means to an electrical control signal means for establishing said drain current, and trimming said balancing resistance means under conditions of said drain current to establish essentially equal turn-on of said devices and thereby load current flow in each of said devices.
Claim 7
Dependent Claim
67 words
The method of claim 4 wherein a plurality of said power circuits are fabricated as individual modules, each of said MOSFET devices fabricated with said balancing resistance means formed as a thick film resistor between the gate and the source, and said trimming of said balancing resistance means including laser trimming of said thick film resistors whereby each of said individual modules have essentially identical operating characteristics.
Claim 8
Dependent Claim
49 words
The method of claim 4 wherein said MOFSET devices are selected to operate within a selected narrow input threshold voltage range, operating said power circuit at a voltage slightly greater than said range, and trimming said balancing resistance means to establish a threshold voltage within said threshold voltage range.
Claim 9
Independent Claim
68 words
The method of balancing load currents in a power circuit having parallel connected FET devices each having a gate and a source and a drain and each having a balancing resistor connected between the gate and source, comprising operating said power circuit under load conditions, and adjusting the ohmic values of said balancing resistors while under said load conditions to establish balanced current distribution through said FET devices.
Claim 10
Independent Claim
68 words
The method of balancing load currents in a power circuit having parallel connected FET devices each having a gate and a source and a drain and each having a balancing resistor connected between the gate and source, comprising operating said power circuit under load conditions, and adjusting the ohmic values of said balancing resistors while under said load conditions to establish balanced current distribution through said FET devices.
Claim 11
Dependent Claim
177 words
In a pulsed power circuit having a pulsed inductive load means connected in series with a high power variable ballast element, said ballast element comprising a plurality of power hybrid modules each having load terminals connected in common to said load means and to a common reference connection and a control terminal connected in common to a common control connection, each of said power hybrid modules having essentially corresponding current sharing characteristics and each of said modules comprising a plurality of parallel connected MOSFETs, each of said MOSFETs having a drain connected in common to one of said load terminals and having a source connected in series with a source resistor to a source common connected to the other of said load terminals and each having a gate connected in series with a gate resistor to a gate common connected to the control terminal, each of said MOSFETs including a balancing resistor connected between said gate and said source and each resistor having a resistance to establish simultaneous turn-on and essentially balance current flow through said MOSFETs.
Claim 12
Dependent Claim
177 words
In a pulsed power circuit having a pulsed inductive load means connected in series with a high power variable ballast element, said ballast element comprising a plurality of power hybrid modules each having load terminals connected in common to said load means and to a common reference connection and a control terminal connected in common to a common control connection, each of said power hybrid modules having essentially corresponding current sharing characteristics and each of said modules comprising a plurality of parallel connected MOSFETs, each of said MOSFETs having a drain connected in common to one of said load terminals and having a source connected in series with a source resistor to a source common connected to the other of said load terminals and each having a gate connected in series with a gate resistor to a gate common connected to the control terminal, each of said MOSFETs including a balancing resistor connected between said gate and said source and each resistor having a resistance to establish simultaneous turn-on and essentially balance current flow through said MOSFETs.
Claim 13
Dependent Claim
23 words
The pulsed power circuit of claim 8 wherein said power circuit operates at 400 volts DC and a maximum 32 amperes per module.
Claim 14
Dependent Claim
134 words
A power MOSFET comprising, a MOSFET chip adapted to be connected in parallel and having a drain terminal and a source terminal connected in series with a source resistor and a gate terminal connected in series with a gate resistor and having an internal gate-to-source resistance, a balancing resistor connecting said gate terminal to said source terminal to form a circuit unit, and said balancing resistor having a resistance related to the internal gate-to-source resistance to establish a predetermined threshold voltage for the chip, and said chip connected in circuit with other similar chips each having a similar balancing resistor and with said chip and said other similar chips connected in parallel and with a common input signal connected to each of said gate resistors to establish equal distribution of the total current flow.
Claim 15
Dependent Claim
134 words
A power MOSFET comprising, a MOSFET chip adapted to be connected in parallel and having a drain terminal and a source terminal connected in series with a source resistor and a gate terminal connected in series with a gate resistor and having an internal gate-to-source resistance, a balancing resistor connecting said gate terminal to said source terminal to form a circuit unit, and said balancing resistor having a resistance related to the internal gate-to-source resistance to establish a predetermined threshold voltage for the chip, and said chip connected in circuit with other similar chips each having a similar balancing resistor and with said chip and said other similar chips connected in parallel and with a common input signal connected to each of said gate resistors to establish equal distribution of the total current flow.
References Cited (Backward Citations)
US4247824A
Cited
US4554512A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-18 | 1992-04-18 | 1992-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-18 | 1996-04-18 | 1996-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-18 | 2000-04-18 | 2000-10-18 | $7700.00 | Window Closed / Lapsed |