Patent US4779041A successfully refreshed from Google Patents.
← Back to Patent Explorer
US4779041A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated circuit transfer test device system

Assignee: Agilent Technologies Inc
•
Filing: 1987-05-20
•
Granted: 1988-10-18
•
Expires: 2007-05-20
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract The system is for testing semiconductor components such as TTL components and CMOS components to determine whether the input, output and ground pins are conductively connected to a circuit, such as the circuit of a printed circuit board, and whether proper conductive paths exist between the connector pins and the ground pin through the semiconductor. This is accomplished by providing a current pulse on one terminal to generate a voltage drop across an inherent resistance of the component which is connected in series with the other terminal of the component and detecting the resulting voltage drop. The existence of the voltage drop indicates that both the input and output terminals, as well as the ground terminal, are properly connected to the printed circuit board.

Inventors

  • 👤 Eddie L. Williamson, Jr.

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 21:12
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2801; G01R31/281; G01R31/2812

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 288 words
A system for testing a semiconductor component to determine whether input and output connector pins and a ground pin of said semiconductor component are conductively connected to a circuit and whether proper conductive paths exist between said connector pins and said ground pin through said semiconductor comprising: first current source means for generating a biasing current sufficient to activate a diode junction between said input connector pin and said ground pin; first conductor means for forming a conductive path from said first current source means to a point on said circuit which is designed to be conductively coupled to said input connector pin; second current source means for generating a testing current that is sufficient to cause a voltage drop on said first conductor means in response to said testing current flowing through a common inherent resistance of said semiconductor component that is connected in series from said ground pin to both said input and output connector pins; second conductor means for forming a conductive path from said second current source means to a point on said circuit which is designed to be conductively coupled to said output connector pin; third conductor means for forming a conductive path from ground potential in said circuit to said ground pin; detector means for measuring said voltage drop whenever said first conductor means is conductively connected to said input connector pin, said second conductor means is conductively connected to said output connector pin and said third conductor means is conductively connected to said ground pin indicating that said input and output connector pins and said ground pin are conductively connected to said circuit and that proper conductive paths exist between said connector pins and said ground pin through said semiconductor component.
Claim 2
Independent Claim 288 words
A system for testing a semiconductor component to determine whether input and output connector pins and a ground pin of said semiconductor component are conductively connected to a circuit and whether proper conductive paths exist between said connector pins and said ground pin through said semiconductor comprising: first current source means for generating a biasing current sufficient to activate a diode junction between said input connector pin and said ground pin; first conductor means for forming a conductive path from said first current source means to a point on said circuit which is designed to be conductively coupled to said input connector pin; second current source means for generating a testing current that is sufficient to cause a voltage drop on said first conductor means in response to said testing current flowing through a common inherent resistance of said semiconductor component that is connected in series from said ground pin to both said input and output connector pins; second conductor means for forming a conductive path from said second current source means to a point on said circuit which is designed to be conductively coupled to said output connector pin; third conductor means for forming a conductive path from ground potential in said circuit to said ground pin; detector means for measuring said voltage drop whenever said first conductor means is conductively connected to said input connector pin, said second conductor means is conductively connected to said output connector pin and said third conductor means is conductively connected to said ground pin indicating that said input and output connector pins and said ground pin are conductively connected to said circuit and that proper conductive paths exist between said connector pins and said ground pin through said semiconductor component.
Claim 3
Dependent Claim 17 words
The system of claim 1 wherein said semiconductor component comprises a transistor to transistor logic (TTL) device.
Claim 4
Dependent Claim 15 words
The system of claim 1 wherein said semiconductor component comprises a metal oxide semiconductor device.
Claim 5
Dependent Claim 21 words
The system of claim 1 further comprising: guarding means for eliminating conductive paths between said first conductor and said second conductor.
Claim 6
Independent Claim 287 words
A system for testing a semiconductor component to determine whether input and output connector pins and ground pin of said semiconductor component are conductively connected to a circuit and whether proper conductive paths exist between said connector pins and said ground pin through said semicondcutor comprising: first current source means for generating a biasing current sufficient to activate a diode junction between said output connector pin and said ground pin; first conductor means for forming a conductive path from said first current source means to a point on said circuit which is designed to be conductively coupled to said output connector pin; second current source means for generating a testing current that is sufficient to cause a voltage drop on said first conductor means in response to said testing current flowing through a common inherent resistance of said semiconductor component that is connected in series from said ground pin to both said input and output connector pins; second conductor means for forming a conductive path from said second current source means to a point on said circuit which is designed to be conductively coupled to said input connector pin; third conductor means for forming a conductive path from ground potential in said circuit to said ground pin; detector means for measuring said voltage drop whenever said first conductor means is conductively connected to said output connector pin, said second conductor means is conductively connected to said input connector pin and said third conductor means is conductively connected to said ground pin indicating that said input and output connector pins and said ground pin are conductively connected to said circuit and that proper conductive paths exist between said connector pins and said ground pin through said semiconductor component.
Claim 7
Independent Claim 287 words
A system for testing a semiconductor component to determine whether input and output connector pins and ground pin of said semiconductor component are conductively connected to a circuit and whether proper conductive paths exist between said connector pins and said ground pin through said semicondcutor comprising: first current source means for generating a biasing current sufficient to activate a diode junction between said output connector pin and said ground pin; first conductor means for forming a conductive path from said first current source means to a point on said circuit which is designed to be conductively coupled to said output connector pin; second current source means for generating a testing current that is sufficient to cause a voltage drop on said first conductor means in response to said testing current flowing through a common inherent resistance of said semiconductor component that is connected in series from said ground pin to both said input and output connector pins; second conductor means for forming a conductive path from said second current source means to a point on said circuit which is designed to be conductively coupled to said input connector pin; third conductor means for forming a conductive path from ground potential in said circuit to said ground pin; detector means for measuring said voltage drop whenever said first conductor means is conductively connected to said output connector pin, said second conductor means is conductively connected to said input connector pin and said third conductor means is conductively connected to said ground pin indicating that said input and output connector pins and said ground pin are conductively connected to said circuit and that proper conductive paths exist between said connector pins and said ground pin through said semiconductor component.
Claim 8
Dependent Claim 21 words
The system of claim 5 further comprising: guarding means for eliminating conductive paths between said first conductor and said second conductor.
Claim 9
Independent Claim 171 words
A method of testing a semiconductor component to determine whether input and output connector pins and a ground pin of said semiconductor component are conductively connected to a circuit and whether proper conductive paths exist between said connector pins and said ground pin through said semiconductor comprising the steps of: applying a biasing current to a first conductor of said circuit which is coupled to an input lead of said digital component that is sufficient to forward bias a diode junction that exists between said input lead and a ground lead of said semiconductor component; applying a testing current to a second conductor of said circuit which is coupled to an output lead of said semiconductor component that is sufficient to cause a detectable voltage drop between a third conductor which is coupled to said ground lead and said first conductor, said detectable voltage drop resulting from said testing current flowing through an inherent resistance of said digital component that is connected in series to both said first and second leads.
Claim 10
Independent Claim 171 words
A method of testing a semiconductor component to determine whether input and output connector pins and a ground pin of said semiconductor component are conductively connected to a circuit and whether proper conductive paths exist between said connector pins and said ground pin through said semiconductor comprising the steps of: applying a biasing current to a first conductor of said circuit which is coupled to an input lead of said digital component that is sufficient to forward bias a diode junction that exists between said input lead and a ground lead of said semiconductor component; applying a testing current to a second conductor of said circuit which is coupled to an output lead of said semiconductor component that is sufficient to cause a detectable voltage drop between a third conductor which is coupled to said ground lead and said first conductor, said detectable voltage drop resulting from said testing current flowing through an inherent resistance of said digital component that is connected in series to both said first and second leads.
Claim 11
Dependent Claim 48 words
The method of claim 7 further comprising the step of: guarding parallel conductive paths between said first conductor and said second conductor by grounding said parallel conductive paths to ensure that said voltage drop on said first conductor results from said testing current flowing through said inherent resistance.
Claim 12
Independent Claim 170 words
A method of testing a semiconductor component to determine whether input and output connector pins and a ground pin of said semiconductor component are conductively connected to a circuit and whether proper conductive paths exist between said connector pins and said ground pin through said semiconductor comprising the steps of: applying a biasing current to a first conductor of said circuit which is coupled to an output lead of said digital component that is sufficient to forward bias a diode junction that exists between said first lead output and a ground lead of said semiconductor; applying a testing current to a second conductor of said circuit which is coupled to an input lead of said semiconductor that is sufficient to cause a detectable voltage drop between a third conductor which is coupled to said ground lead and said first conductor, said detectable voltage drop resulting from said testing current flowing through an inherent resistance of said digital component that is connected in series to both said first and second leads.
Claim 13
Independent Claim 170 words
A method of testing a semiconductor component to determine whether input and output connector pins and a ground pin of said semiconductor component are conductively connected to a circuit and whether proper conductive paths exist between said connector pins and said ground pin through said semiconductor comprising the steps of: applying a biasing current to a first conductor of said circuit which is coupled to an output lead of said digital component that is sufficient to forward bias a diode junction that exists between said first lead output and a ground lead of said semiconductor; applying a testing current to a second conductor of said circuit which is coupled to an input lead of said semiconductor that is sufficient to cause a detectable voltage drop between a third conductor which is coupled to said ground lead and said first conductor, said detectable voltage drop resulting from said testing current flowing through an inherent resistance of said digital component that is connected in series to both said first and second leads.
Claim 14
Dependent Claim 48 words
The method of claim 9 further comprising the step of: guarding parallel conductive paths between said first conductor and said second conductor by grounding said parallel conductive paths to ensure that said voltage drop on said first conductor results from said testing current flowing through said inherent resistance.

References Cited (Backward Citations)

US3969670A Cited
GB2038490A Cited
US4595875A Cited
US4670708A Cited
GB2167196A Cited
US4727317A Cited
US4697139A Cited
US4638243A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-10-18 1992-04-18 1992-10-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-10-18 1996-04-18 1996-10-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-10-18 2000-04-18 2000-10-18 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag