Gate array circuit for decoding circuits

Claim 2

A decoder circuit for decoding different combinations of supplied original input signals on input signal lines, comprising at least one predecode circuit coupled to said input signal lines for producing predecoded output signals on output lines of said predecode circuit, and a plurality of decoder units including at least one decoder unit coupled to at least two different combinations of said input signal lines, and at least one decoder unit coupled to the combination of at least one of said output lines and at least one of said input signal lines.

Claim 3

A decoder circuit for decoding different combinations of supplied original input signals on input signal lines, comprising at least one predecode circuit coupled to said input signal lines for producing predecoded output signals on output lines of said predecode circuit, and a plurality of decoder units including at least one decoder unit coupled to at least two different combinations of said input signal lines, at least one decoder unit coupled to selected ones of said output signal lines alone and a decoder unit coupled to at least one of said output signal lines and at least one of said input signal lines.

Claim 4

A decoder circuit for decoding different combinations of supplied original input signals on input signal lines, comprising at least one predecode circuit coupled to said input signal lines for producing predecoded output signals on output lines of said predecode circuit, and a plurality of decoder units including at least one decoder unit coupled to at least two different combinations of said input signal lines, at least one decoder unit coupled to selected ones of said output signal lines alone and a decoder unit coupled to at least one of said output signal lines and at least one of said input signal lines.

Claim 5

A decoder circuit as set forth in claim 1 or 2, in which each of said plurality of decoder units comprises a logic NAND gate.

Claim 6

A semiconductor decoder circuit including a plurality of decoder units for decoding different combinations of supplied original input signals on input signal lines, comprising: a first set of signal lines formed on a semiconductor structure, the first set of signal lines comprising a first group of signal lines connected to a source of a first predetermined voltage and a second group of signal lines connected to a source of a second predetermined voltage, a second set of signal lines formed on a semiconductor structure and extending substantially at right angles to said first set of signal lines, the second set of signal lines comprising a third group of signal lines respectively coupled to output signal lines having output signals predecoded from the input signals on selected ones of said input signal lines and a fourth group of signal lines respectively coupled to the input signals on selected ones of said input signal lines, a first set of field-effect transistors selectively connected in series to the source of said first predetermined voltage along each of the signal lines of said first predetermined voltage along each of the signal lines of said first group, each of the first set of field-effect transistors being of one channel conductivity type, and a second set of field-effect transistors selectively connected in parallel to the source of said second predetermined voltage along each of the signal lines of said second group, each of the second set of field-effect transistors being of the channel conductivity type opposite to said one channel conductivity type, the second set of field-effect transistors having their gates selectively connected to the signal lines of said third and fourth groups, the first set of field-effect transistors arranged along each of the signal lines of said first group and the second set of field-effect transistors arranged along each of the signal lines of said second group implementing each of said decoder units.

Claim 7

A semiconductor decoder circuit including a plurality of decoder units for decoding different combinations of supplied original input signals on input signal lines, comprising: a first set of signal lines formed on a semiconductor structure, the first set of signal lines comprising a first group of signal lines connected to a source of a first predetermined voltage and a second group of signal lines connected to a source of a second predetermined voltage, a second set of signal lines formed on a semiconductor structure and extending substantially at right angles to said first set of signal lines, the second set of signal lines comprising a third group of signal lines respectively coupled to output signal lines having output signals predecoded from the input signals on selected ones of said input signal lines and a fourth group of signal lines respectively coupled to the input signals on selected ones of said input signal lines, a first set of field-effect transistors selectively connected in series to the source of said first predetermined voltage along each of the signal lines of said first predetermined voltage along each of the signal lines of said first group, each of the first set of field-effect transistors being of one channel conductivity type, and a second set of field-effect transistors selectively connected in parallel to the source of said second predetermined voltage along each of the signal lines of said second group, each of the second set of field-effect transistors being of the channel conductivity type opposite to said one channel conductivity type, the second set of field-effect transistors having their gates selectively connected to the signal lines of said third and fourth groups, the first set of field-effect transistors arranged along each of the signal lines of said first group and the second set of field-effect transistors arranged along each of the signal lines of said second group implementing each of said decoder units.