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Forming a split-level CMOS device

Assignee: Texas Instruments Inc
•
Filing: 1987-12-30
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Granted: 1988-10-11
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Expires: 2007-12-30
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Abstract

Abstract A method for forming CMOS device wherein the NMOS devices are bulk devices and the PMOS devices are SOI devices. The PMOS devices are formed with their channel regions in a silicon-on-insulator layer, preferably a laterally recrystallized annealed-polysilicon layer over a silicon dioxide layer.

Inventors

  • 👤 David B. Scott
  • 👤 Satwinder S. Malhi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 18:29
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01

Claims Analysis

Total Claims: 17
Claim 1
Independent Claim 133 words
A method of forming a CMOS integrated circuit, comprising: (a) providing a single crystal silicon substrate; (b) forming a first field oxide region in said substrate to provide a moat region; (c) forming a polysilicon layer over said moat region in contact with said substrate and extending over and in contact with said first field oxide region; (d) converting all of said polysilicon layer to single crystal type; (e) forming a channel region of a first conductivity type in said polysilicon layer over said first field oxide region; (f) forming a channel region of opposite conductivity type in said polysilicon layer over said moat region; one of the source/drain regions of said last mentioned device extending over said first field oxide; and (g) forming gate regions over and insulated from said channel region.
Claim 2
Independent Claim 133 words
A method of forming a CMOS integrated circuit, comprising: (a) providing a single crystal silicon substrate; (b) forming a first field oxide region in said substrate to provide a moat region; (c) forming a polysilicon layer over said moat region in contact with said substrate and extending over and in contact with said first field oxide region; (d) converting all of said polysilicon layer to single crystal type; (e) forming a channel region of a first conductivity type in said polysilicon layer over said first field oxide region; (f) forming a channel region of opposite conductivity type in said polysilicon layer over said moat region; one of the source/drain regions of said last mentioned device extending over said first field oxide; and (g) forming gate regions over and insulated from said channel region.
Claim 3
Dependent Claim 16 words
The method of claim 1 wherein step (b) is formed by local oxidation of silicon (LOCOS).
Claim 4
Dependent Claim 14 words
The method of claim 2 wherein said polysilicon layer in step (c) is undoped.
Claim 5
Dependent Claim 14 words
The method of claim 3 wherein step (d) comprises annealing of said polysilicon layer.
Claim 6
Dependent Claim 19 words
The method of claim 4 wherein said first conductivity type is N-type and said opposite conductivity type is P-type.
Claim 7
Dependent Claim 19 words
The method of claim 3 wherein said first conductivity type is N-type and said opposite conductivity type is P-type.
Claim 8
Dependent Claim 14 words
The method of claim 2 wherein step (d) comprises annealing of said polysilicon layer.
Claim 9
Dependent Claim 19 words
The method of claim 7 wherein said first conductivity type is N-type and said opposite conductivity type is P-type.
Claim 10
Dependent Claim 19 words
The method of claim 2 wherein said first conductivity type is N-type and said opposite conductivity type is P-type.
Claim 11
Dependent Claim 14 words
The method of claim 1 wherein said polysilicon layer in step (c) is undoped.
Claim 12
Dependent Claim 14 words
The method of claim 10 wherein step (d) comprises annealing of said polysilicon layer.
Claim 13
Dependent Claim 19 words
The method of claim 11 wherein said first conductivity type is N-type and said opposite conductivity type is P-type.
Claim 14
Dependent Claim 19 words
The method of claim 10 wherein said first conductivity type is N-type and said opposite conductivity type is P-type.
Claim 15
Dependent Claim 14 words
The method of claim 1 wherein step (d) comprises annealing of said polysilicon layer.
Claim 16
Dependent Claim 19 words
The method of claim 14 wherein said first conductivity type is N-type and said opposite conductivity type is P-type.
Claim 17
Dependent Claim 19 words
The method of claim 1 wherein said first conductivity type is N-type and said opposite conductivity type is P-type.

References Cited (Backward Citations)

JPS5497384A Cited
US4333099A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-10-11 1992-04-11 1992-10-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-10-11 1996-04-11 1996-10-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-10-11 2000-04-11 2000-10-11 $7700.00 Window Closed / Lapsed

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